1 From e3c707d23a3a5bc1ba9b8c03731a32c3714ae56a Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 31 Aug 2022 19:05:20 +0800
4 Subject: [PATCH 28/32] cpu: add basic cpu driver for MediaTek ARM chips
6 Add basic CPU driver used to retrieve CPU model information.
8 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
10 drivers/cpu/Makefile | 1 +
11 drivers/cpu/mtk_cpu.c | 106 ++++++++++++++++++++++++++++++++++++++++++
12 2 files changed, 107 insertions(+)
13 create mode 100644 drivers/cpu/mtk_cpu.c
15 --- a/drivers/cpu/Makefile
16 +++ b/drivers/cpu/Makefile
17 @@ -9,6 +9,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
18 obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
19 obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
20 obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
21 +obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
22 obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
23 obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
24 obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
26 +++ b/drivers/cpu/mtk_cpu.c
28 +// SPDX-License-Identifier: GPL-2.0
30 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
32 + * Author: Weijie Gao <weijie.gao@mediatek.com>
35 +#include <linux/types.h>
38 +#include <fdt_support.h>
40 +#include <asm/global_data.h>
41 +#include <linux/io.h>
43 +DECLARE_GLOBAL_DATA_PTR;
45 +struct mtk_cpu_plat {
46 + void __iomem *hwver_base;
49 +static int mtk_cpu_get_desc(const struct udevice *dev, char *buf, int size)
51 + struct mtk_cpu_plat *plat = dev_get_plat(dev);
53 + snprintf(buf, size, "MediaTek MT%04X", readl(plat->hwver_base));
58 +static int mtk_cpu_get_count(const struct udevice *dev)
63 +static int mtk_cpu_get_vendor(const struct udevice *dev, char *buf, int size)
65 + snprintf(buf, size, "MediaTek");
70 +static int mtk_cpu_probe(struct udevice *dev)
72 + struct mtk_cpu_plat *plat = dev_get_plat(dev);
73 + const void *fdt = gd->fdt_blob, *reg;
74 + int offset, parent, len, na, ns;
80 + offset = fdt_path_offset(fdt, "/hwver");
84 + parent = fdt_parent_offset(fdt, offset);
88 + na = fdt_address_cells(fdt, parent);
92 + ns = fdt_size_cells(gd->fdt_blob, parent);
96 + reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
101 + addr = fdt_translate_address(fdt, offset, reg);
103 + addr = fdt_read_number(reg, na);
105 + plat->hwver_base = map_sysmem(addr, 0);
106 + if (!plat->hwver_base)
112 +static const struct cpu_ops mtk_cpu_ops = {
113 + .get_desc = mtk_cpu_get_desc,
114 + .get_count = mtk_cpu_get_count,
115 + .get_vendor = mtk_cpu_get_vendor,
118 +static const struct udevice_id mtk_cpu_ids[] = {
119 + { .compatible = "arm,cortex-a7" },
120 + { .compatible = "arm,cortex-a53" },
121 + { .compatible = "arm,cortex-a73" },
125 +U_BOOT_DRIVER(cpu_mtk) = {
128 + .of_match = mtk_cpu_ids,
129 + .ops = &mtk_cpu_ops,
130 + .probe = mtk_cpu_probe,
131 + .plat_auto = sizeof(struct mtk_cpu_plat),
132 + .flags = DM_FLAG_PRE_RELOC,