2 #include <asm/arch/sysctl.h>
3 #include <asm/arch/pinmux.h>
4 #include <asm/arch/clock.h>
6 void reset_cpu(ulong addr
)
10 // Assert reset to cores as per power on defaults
11 // Don't touch the DDR interface as things will come to an impromptu stop
12 // NB Possibly should be asserting reset for PLLB, but there are timing
13 // concerns here according to the docs
16 BIT(SYS_CTRL_RST_COPRO
) |
17 BIT(SYS_CTRL_RST_USBHS
) |
18 BIT(SYS_CTRL_RST_USBHSPHYA
) |
19 BIT(SYS_CTRL_RST_MACA
) |
20 BIT(SYS_CTRL_RST_PCIEA
) |
21 BIT(SYS_CTRL_RST_SGDMA
) |
22 BIT(SYS_CTRL_RST_CIPHER
) |
23 BIT(SYS_CTRL_RST_SATA
) |
24 BIT(SYS_CTRL_RST_SATA_LINK
) |
25 BIT(SYS_CTRL_RST_SATA_PHY
) |
26 BIT(SYS_CTRL_RST_PCIEPHY
) |
27 BIT(SYS_CTRL_RST_STATIC
) |
28 BIT(SYS_CTRL_RST_UART1
) |
29 BIT(SYS_CTRL_RST_UART2
) |
30 BIT(SYS_CTRL_RST_MISC
) |
31 BIT(SYS_CTRL_RST_I2S
) |
32 BIT(SYS_CTRL_RST_SD
) |
33 BIT(SYS_CTRL_RST_MACB
) |
34 BIT(SYS_CTRL_RST_PCIEB
) |
35 BIT(SYS_CTRL_RST_VIDEO
) |
36 BIT(SYS_CTRL_RST_USBHSPHYB
) |
37 BIT(SYS_CTRL_RST_USBDEV
);
39 writel(value
, SYS_CTRL_RST_SET_CTRL
);
41 // Release reset to cores as per power on defaults
42 writel(BIT(SYS_CTRL_RST_GPIO
), SYS_CTRL_RST_CLR_CTRL
);
44 // Disable clocks to cores as per power-on defaults - must leave DDR
45 // related clocks enabled otherwise we'll stop rather abruptly.
47 BIT(SYS_CTRL_CLK_COPRO
) |
48 BIT(SYS_CTRL_CLK_DMA
) |
49 BIT(SYS_CTRL_CLK_CIPHER
) |
50 BIT(SYS_CTRL_CLK_SD
) |
51 BIT(SYS_CTRL_CLK_SATA
) |
52 BIT(SYS_CTRL_CLK_I2S
) |
53 BIT(SYS_CTRL_CLK_USBHS
) |
54 BIT(SYS_CTRL_CLK_MAC
) |
55 BIT(SYS_CTRL_CLK_PCIEA
) |
56 BIT(SYS_CTRL_CLK_STATIC
) |
57 BIT(SYS_CTRL_CLK_MACB
) |
58 BIT(SYS_CTRL_CLK_PCIEB
) |
59 BIT(SYS_CTRL_CLK_REF600
) |
60 BIT(SYS_CTRL_CLK_USBDEV
);
62 writel(value
, SYS_CTRL_CLK_CLR_CTRL
);
64 // Enable clocks to cores as per power-on defaults
66 // Set sys-control pin mux'ing as per power-on defaults
68 writel(0, SYS_CONTROL_BASE
+ PINMUX_SECONDARY_SEL
);
69 writel(0, SYS_CONTROL_BASE
+ PINMUX_TERTIARY_SEL
);
70 writel(0, SYS_CONTROL_BASE
+ PINMUX_QUATERNARY_SEL
);
71 writel(0, SYS_CONTROL_BASE
+ PINMUX_DEBUG_SEL
);
72 writel(0, SYS_CONTROL_BASE
+ PINMUX_ALTERNATIVE_SEL
);
73 writel(0, SYS_CONTROL_BASE
+ PINMUX_PULLUP_SEL
);
75 writel(0, SEC_CONTROL_BASE
+ PINMUX_SECONDARY_SEL
);
76 writel(0, SEC_CONTROL_BASE
+ PINMUX_TERTIARY_SEL
);
77 writel(0, SEC_CONTROL_BASE
+ PINMUX_QUATERNARY_SEL
);
78 writel(0, SEC_CONTROL_BASE
+ PINMUX_DEBUG_SEL
);
79 writel(0, SEC_CONTROL_BASE
+ PINMUX_ALTERNATIVE_SEL
);
80 writel(0, SEC_CONTROL_BASE
+ PINMUX_PULLUP_SEL
);
82 // No need to save any state, as the ROM loader can determine whether reset
83 // is due to power cycling or programatic action, just hit the (self-
84 // clearing) CPU reset bit of the block reset register
86 BIT(SYS_CTRL_RST_SCU
) |
87 BIT(SYS_CTRL_RST_ARM0
) |
88 BIT(SYS_CTRL_RST_ARM1
);
90 writel(value
, SYS_CTRL_RST_SET_CTRL
);