f93cc9ca58e9b8b8d99ec37ffb17b463b0263d44
7 #include <asm/arch/spl.h>
8 #include <asm/arch/pinmux.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/sysctl.h>
12 DECLARE_GLOBAL_DATA_PTR
;
14 #ifdef CONFIG_SPL_BUILD
17 #define DILIGENCE (1048576/4)
18 static int test_memory(u32 memory
)
22 const u32 INIT_PATTERN
= 0xAA55AA55;
23 const u32 INC_PATTERN
= 0x01030507;
29 read
= write
= (volatile u32
*) memory
;
30 pattern
= INIT_PATTERN
;
31 for (i
= 0; i
< DILIGENCE
; i
++) {
33 pattern
+= INC_PATTERN
;
36 pattern
= INIT_PATTERN
;
37 for (i
= 0; i
< DILIGENCE
; i
++) {
38 check
+= (pattern
== *read
++) ? 1 : 0;
39 pattern
+= INC_PATTERN
;
41 return (check
== DILIGENCE
) ? 0 : -1;
48 reset_block(SYS_CTRL_RST_UART1
, 1);
50 reset_block(SYS_CTRL_RST_UART1
, 0);
53 /* Setup pin mux'ing for UART1 */
54 pinmux_set(PINMUX_BANK_MFA
, 30, PINMUX_UARTA_SIN
);
55 pinmux_set(PINMUX_BANK_MFA
, 31, PINMUX_UARTA_SOUT
);
58 extern void init_ddr(int mhz
);
60 void board_inithw(void)
69 preloader_console_init();
71 plla_freq
= plla_set_config(CONFIG_PLLA_FREQ_MHZ
);
75 if(test_memory(CONFIG_SYS_SDRAM_BASE
)) {
76 puts("memory test failed\n");
78 puts("memory test done\n");
81 #ifdef CONFIG_SPL_BSS_DRAM_START
82 extern char __bss_dram_start
[];
83 extern char __bss_dram_end
[];
84 memset(&__bss_dram_start
, 0, __bss_dram_end
- __bss_dram_start
);
88 void board_init_f(ulong dummy
)
90 /* Set the stack pointer. */
91 asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK
));
94 memset(__bss_start
, 0, __bss_end
- __bss_start
);
96 /* Set global data pointer. */
101 board_init_r(NULL
, 0);
104 u32
spl_boot_device(void)
106 return CONFIG_SPL_BOOT_DEVICE
;
109 #ifdef CONFIG_SPL_BLOCK_SUPPORT
110 void spl_block_device_init(void)
116 #ifdef CONFIG_SPL_OS_BOOT
117 int spl_start_uboot(void)
119 /* break into full u-boot on 'c' */
120 return (serial_tstc() && serial_getc() == 'c');
124 void spl_display_print(void)
126 /* print a hint, so that we will not use the wrong SPL by mistake */
127 puts(" Boot device: " BOOT_DEVICE_TYPE
"\n" );
130 void lowlevel_init(void)
135 /* quick and dirty memory allocation */
136 static ulong next_mem
= CONFIG_SPL_MALLOC_START
;
138 void *memalign(size_t alignment
, size_t bytes
)
140 ulong mem
= ALIGN(next_mem
, alignment
);
142 next_mem
= mem
+ bytes
;
144 if (next_mem
> CONFIG_SYS_SDRAM_BASE
+ CONFIG_MIN_SDRAM_SIZE
) {
145 printf("spl: out of memory\n");
157 #endif /* CONFIG_SPL_BUILD */
159 int board_early_init_f(void)
164 #define STATIC_CTL_BANK0 (STATIC_CONTROL_BASE + 4)
165 #define STATIC_READ_CYCLE_SHIFT 0
166 #define STATIC_DELAYED_OE (1 << 7)
167 #define STATIC_WRITE_CYCLE_SHIFT 8
168 #define STATIC_WRITE_PULSE_SHIFT 16
169 #define STATIC_WRITE_BURST_EN (1 << 23)
170 #define STATIC_TURN_AROUND_SHIFT 24
171 #define STATIC_BUFFER_PRESENT (1 << 28)
172 #define STATIC_READ_BURST_EN (1 << 29)
173 #define STATIC_BUS_WIDTH8 (0 << 30)
174 #define STATIC_BUS_WIDTH16 (1 << 30)
175 #define STATIC_BUS_WIDTH32 (2 << 30)
177 void nand_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
179 struct nand_chip
*this = mtd
->priv
;
180 unsigned long nandaddr
= (unsigned long) this->IO_ADDR_W
;
182 if (ctrl
& NAND_CTRL_CHANGE
) {
183 nandaddr
&= ~(BIT(NAND_ALE_ADDR_PIN
) | BIT(NAND_CLE_ADDR_PIN
));
185 nandaddr
|= BIT(NAND_CLE_ADDR_PIN
);
186 else if (ctrl
& NAND_ALE
)
187 nandaddr
|= BIT(NAND_ALE_ADDR_PIN
);
188 this->IO_ADDR_W
= (void __iomem
*) nandaddr
;
191 if (cmd
!= NAND_CMD_NONE
)
192 writeb(cmd
, (void __iomem
*) nandaddr
);
195 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
197 int nand_dev_ready(struct mtd_info
*mtd
)
199 struct nand_chip
*chip
= mtd
->priv
;
201 udelay(chip
->chip_delay
);
206 void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
209 struct nand_chip
*chip
= mtd
->priv
;
211 for (i
= 0; i
< len
; i
++)
212 buf
[i
] = readb(chip
->IO_ADDR_R
);
215 void nand_dev_reset(struct nand_chip
*chip
)
217 writeb(NAND_CMD_RESET
, chip
->IO_ADDR_W
+ BIT(NAND_CLE_ADDR_PIN
));
218 udelay(chip
->chip_delay
);
219 writeb(NAND_CMD_STATUS
, chip
->IO_ADDR_W
+ BIT(NAND_CLE_ADDR_PIN
));
220 while (!(readb(chip
->IO_ADDR_R
) & NAND_STATUS_READY
)) {
227 #define nand_dev_reset(chip) /* framework will reset the chip anyway */
228 #define nand_read_buf NULL /* framework will provide a default one */
229 #define nand_dev_ready NULL /* dev_ready is optional */
233 int board_nand_init(struct nand_chip
*chip
)
235 /* Block reset Static core */
236 reset_block(SYS_CTRL_RST_STATIC
, 1);
237 reset_block(SYS_CTRL_RST_STATIC
, 0);
239 /* Enable clock to Static core */
240 enable_clock(SYS_CTRL_CLK_STATIC
);
242 /* enable flash support on static bus.
243 * Enable static bus onto GPIOs, only CS0 */
244 pinmux_set(PINMUX_BANK_MFA
, 12, PINMUX_STATIC_DATA0
);
245 pinmux_set(PINMUX_BANK_MFA
, 13, PINMUX_STATIC_DATA1
);
246 pinmux_set(PINMUX_BANK_MFA
, 14, PINMUX_STATIC_DATA2
);
247 pinmux_set(PINMUX_BANK_MFA
, 15, PINMUX_STATIC_DATA3
);
248 pinmux_set(PINMUX_BANK_MFA
, 16, PINMUX_STATIC_DATA4
);
249 pinmux_set(PINMUX_BANK_MFA
, 17, PINMUX_STATIC_DATA5
);
250 pinmux_set(PINMUX_BANK_MFA
, 18, PINMUX_STATIC_DATA6
);
251 pinmux_set(PINMUX_BANK_MFA
, 19, PINMUX_STATIC_DATA7
);
253 pinmux_set(PINMUX_BANK_MFA
, 20, PINMUX_STATIC_NWE
);
254 pinmux_set(PINMUX_BANK_MFA
, 21, PINMUX_STATIC_NOE
);
255 pinmux_set(PINMUX_BANK_MFA
, 22, PINMUX_STATIC_NCS
);
256 pinmux_set(PINMUX_BANK_MFA
, 23, PINMUX_STATIC_ADDR18
);
257 pinmux_set(PINMUX_BANK_MFA
, 24, PINMUX_STATIC_ADDR19
);
259 /* Setup the static bus CS0 to access FLASH */
261 writel((0x3f << STATIC_READ_CYCLE_SHIFT
)
262 | (0x3f << STATIC_WRITE_CYCLE_SHIFT
)
263 | (0x1f << STATIC_WRITE_PULSE_SHIFT
)
264 | (0x03 << STATIC_TURN_AROUND_SHIFT
) |
268 chip
->cmd_ctrl
= nand_hwcontrol
;
269 chip
->ecc
.mode
= NAND_ECC_SOFT
;
270 chip
->chip_delay
= 30;
271 chip
->dev_ready
= nand_dev_ready
;
272 chip
->read_buf
= nand_read_buf
;
274 nand_dev_reset(chip
);
281 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
282 gd
->bd
->bi_arch_number
= MACH_TYPE_OXNAS
;
284 /* assume uart is already initialized by SPL */
286 #if defined(CONFIG_START_IDE)
294 /* copied from board/evb64260/sdram_init.c */
296 * Check memory range for valid RAM. A simple memory test determines
297 * the actually available RAM size between addresses `base' and
298 * `base + maxsize'. Some (not all) hardware errors are detected:
299 * - short between address lines
300 * - short between data lines
302 static long int dram_size (long int *base
, long int maxsize
)
304 volatile long int *addr
, *b
= base
;
305 long int cnt
, val
, save1
, save2
;
307 #define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2) /* start test at half size */
308 for (cnt
= STARTVAL
/ sizeof (long); cnt
< maxsize
/ sizeof (long);
310 addr
= base
+ cnt
; /* pointer arith! */
312 save1
= *addr
; /* save contents of addr */
313 save2
= *b
; /* save contents of base */
315 *addr
= cnt
; /* write cnt to addr */
316 *b
= 0; /* put null at base */
318 /* check at base address */
320 *addr
= save1
; /* restore *addr */
321 *b
= save2
; /* restore *b */
324 val
= *addr
; /* read *addr */
330 /* fix boundary condition.. STARTVAL means zero */
331 if (cnt
== STARTVAL
/ sizeof (long))
333 return (cnt
* sizeof (long));
341 gd
->ram_size
= dram_size((long int *)CONFIG_SYS_SDRAM_BASE
,
342 CONFIG_MAX_SDRAM_SIZE
);
346 int board_eth_init(bd_t
*bis
)
350 /* set the pin multiplexers to enable talking to Ethernent Phys */
351 pinmux_set(PINMUX_BANK_MFA
, 3, PINMUX_MACA_MDC
);
352 pinmux_set(PINMUX_BANK_MFA
, 4, PINMUX_MACA_MDIO
);
354 // Ensure the MAC block is properly reset
355 reset_block(SYS_CTRL_RST_MAC
, 1);
357 reset_block(SYS_CTRL_RST_MAC
, 0);
359 // Enable the clock to the MAC block
360 enable_clock(SYS_CTRL_CLK_MAC
);
362 value
= readl(SYS_CTRL_GMAC_CTRL
);
363 /* Use simple mux for 25/125 Mhz clock switching */
364 value
|= BIT(SYS_CTRL_GMAC_SIMPLE_MUX
);
365 /* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
366 value
|= BIT(SYS_CTRL_GMAC_CKEN_GTX
);
367 /* set auto tx speed */
368 value
|= BIT(SYS_CTRL_GMAC_AUTOSPEED
);
370 writel(value
, SYS_CTRL_GMAC_CTRL
);
372 return designware_initialize(MAC_BASE
, PHY_INTERFACE_MODE_RGMII
);