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omap24xx: Remove unmaintained target
[openwrt/staging/mkresin.git] / package / boot / uboot-xburst / patches / 0005-add-nanonote-lcd-support.patch
1 From ca8c5216cfd3ad3fda9867ed2d157ae5a209834b Mon Sep 17 00:00:00 2001
2 From: Xiangfu <xiangfu@openmobilefree.net>
3 Date: Wed, 10 Oct 2012 22:05:27 +0800
4 Subject: [PATCH 5/6] add nanonote lcd support
5
6 ---
7 arch/mips/include/asm/global_data.h | 1 +
8 arch/mips/include/asm/jz4740.h | 90 ++++++++
9 arch/mips/lib/board.c | 6 +
10 common/lcd.c | 9 +-
11 drivers/video/Makefile | 1 +
12 drivers/video/nanonote_gpm940b0.c | 400 +++++++++++++++++++++++++++++++++++
13 drivers/video/nanonote_gpm940b0.h | 135 ++++++++++++
14 include/configs/qi_lb60.h | 7 +
15 include/lcd.h | 52 ++++-
16 9 files changed, 697 insertions(+), 4 deletions(-)
17 create mode 100644 drivers/video/nanonote_gpm940b0.c
18 create mode 100644 drivers/video/nanonote_gpm940b0.h
19
20 diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
21 index cd03d7e..7cec2de 100644
22 --- a/arch/mips/include/asm/global_data.h
23 +++ b/arch/mips/include/asm/global_data.h
24 @@ -44,6 +44,7 @@ typedef struct global_data {
25 unsigned long per_clk; /* Peripheral bus clock */
26 unsigned long mem_clk; /* Memory bus clock */
27 unsigned long dev_clk; /* Device clock */
28 + unsigned long fb_base; /* base address of framebuffer */
29 /* "static data" needed by most of timer.c */
30 unsigned long tbl;
31 unsigned long lastinc;
32 diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
33 index 68287fb..13724a2 100644
34 --- a/arch/mips/include/asm/jz4740.h
35 +++ b/arch/mips/include/asm/jz4740.h
36 @@ -1312,5 +1312,95 @@ do { \
37 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
38 } while (0)
39
40 +/*************************************************************************
41 + * LCD (LCD Controller)
42 + *************************************************************************/
43 +#define REG32(addr) *((volatile u32 *)(addr))
44 +
45 +#define CPM_BASE 0xB0000000
46 +#define CPM_CPCCR (CPM_BASE+0x00)
47 +#define REG_CPM_CPCCR REG32(CPM_CPCCR)
48 +
49 +#define LCD_BASE 0xB3050000
50 +#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
51 +#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
52 +#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
53 +#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
54 +#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
55 +#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
56 +#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
57 +#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
58 +#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
59 +#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
60 +#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
61 +#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
62 +#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
63 +#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
64 +#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
65 +#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
66 +#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
67 +#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
68 +#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
69 +#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
70 +#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
71 +
72 +#define REG_LCD_CFG REG32(LCD_CFG)
73 +#define REG_LCD_VSYNC REG32(LCD_VSYNC)
74 +#define REG_LCD_HSYNC REG32(LCD_HSYNC)
75 +#define REG_LCD_VAT REG32(LCD_VAT)
76 +#define REG_LCD_DAH REG32(LCD_DAH)
77 +#define REG_LCD_DAV REG32(LCD_DAV)
78 +#define REG_LCD_PS REG32(LCD_PS)
79 +#define REG_LCD_CLS REG32(LCD_CLS)
80 +#define REG_LCD_SPL REG32(LCD_SPL)
81 +#define REG_LCD_REV REG32(LCD_REV)
82 +#define REG_LCD_CTRL REG32(LCD_CTRL)
83 +#define REG_LCD_STATE REG32(LCD_STATE)
84 +#define REG_LCD_IID REG32(LCD_IID)
85 +#define REG_LCD_DA0 REG32(LCD_DA0)
86 +#define REG_LCD_SA0 REG32(LCD_SA0)
87 +#define REG_LCD_FID0 REG32(LCD_FID0)
88 +#define REG_LCD_CMD0 REG32(LCD_CMD0)
89 +#define REG_LCD_DA1 REG32(LCD_DA1)
90 +#define REG_LCD_SA1 REG32(LCD_SA1)
91 +#define REG_LCD_FID1 REG32(LCD_FID1)
92 +#define REG_LCD_CMD1 REG32(LCD_CMD1)
93 +
94 +#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
95 +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
96 + #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
97 + #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
98 + #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
99 + #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
100 + #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
101 + #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
102 +
103 +#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
104 +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
105 + #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
106 + #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
107 + #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
108 +#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
109 +#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
110 +#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
111 +#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
112 +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
113 + #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
114 + #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
115 + #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
116 +
117 +#define CPM_LPCDR (CPM_BASE+0x64)
118 +#define CPM_CLKGR (CPM_BASE+0x20)
119 +#define REG_CPM_LPCDR REG32(CPM_LPCDR)
120 +#define REG_CPM_CLKGR REG32(CPM_CLKGR)
121 +
122 +#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
123 +#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
124 +#define __cpm_set_pixdiv(v) \
125 + (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
126 +#define __cpm_set_ldiv(v) \
127 + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
128 +#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
129 +
130 #endif /* !__ASSEMBLY__ */
131 #endif /* __JZ4740_H__ */
132 diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
133 index b14b33e..c2e64d9 100644
134 --- a/arch/mips/lib/board.c
135 +++ b/arch/mips/lib/board.c
136 @@ -172,6 +172,12 @@ void board_init_f(ulong bootflag)
137 addr &= ~(4096 - 1);
138 debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
139
140 +#ifdef CONFIG_LCD
141 + /* reserve memory for LCD display (always full pages) */
142 + addr = lcd_setmem (addr);
143 + gd->fb_base = addr;
144 +#endif /* CONFIG_LCD */
145 +
146 /* Reserve memory for U-Boot code, data & bss
147 * round down to next 16 kB limit
148 */
149 diff --git a/common/lcd.c b/common/lcd.c
150 index b6be800..af1281a 100644
151 --- a/common/lcd.c
152 +++ b/common/lcd.c
153 @@ -263,6 +263,13 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
154 lcd_color_fg : lcd_color_bg;
155 bits <<= 1;
156 }
157 +#elif LCD_BPP == LCD_COLOR32
158 + uint *m = (uint *)d;
159 + for (c=0; c<32; ++c) {
160 + *m++ = (bits & 0x80) ?
161 + lcd_color_fg : lcd_color_bg;
162 + bits <<= 1;
163 + }
164 #endif
165 }
166 #if LCD_BPP == LCD_MONOCHROME
167 @@ -509,7 +516,7 @@ static inline ushort *configuration_get_cmap(void)
168 return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
169 #elif defined(CONFIG_ATMEL_LCD)
170 return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
171 -#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB)
172 +#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB) && !defined(CONFIG_VIDEO_GPM940B0)
173 return panel_info.cmap;
174 #else
175 #if defined(CONFIG_LCD_LOGO)
176 diff --git a/drivers/video/Makefile b/drivers/video/Makefile
177 index ebb6da8..03625bc 100644
178 --- a/drivers/video/Makefile
179 +++ b/drivers/video/Makefile
180 @@ -50,6 +50,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
181 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
182 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
183 COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
184 +COBJS-$(CONFIG_VIDEO_GPM940B0) += nanonote_gpm940b0.o
185
186 COBJS := $(sort $(COBJS-y))
187 SRCS := $(COBJS:.o=.c)
188 diff --git a/drivers/video/nanonote_gpm940b0.c b/drivers/video/nanonote_gpm940b0.c
189 new file mode 100644
190 index 0000000..11efb72
191 --- /dev/null
192 +++ b/drivers/video/nanonote_gpm940b0.c
193 @@ -0,0 +1,400 @@
194 +/*
195 + * JzRISC lcd controller
196 + *
197 + * Xiangfu Liu <xiangfu@sharism.cc>
198 + *
199 + * This program is free software; you can redistribute it and/or
200 + * modify it under the terms of the GNU General Public License as
201 + * published by the Free Software Foundation; either version 2 of
202 + * the License, or (at your option) any later version.
203 + *
204 + * This program is distributed in the hope that it will be useful,
205 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
206 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
207 + * GNU General Public License for more details.
208 + *
209 + * You should have received a copy of the GNU General Public License
210 + * along with this program; if not, write to the Free Software
211 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
212 + * MA 02111-1307 USA
213 + */
214 +
215 +#include <config.h>
216 +#include <common.h>
217 +#include <lcd.h>
218 +
219 +#include <asm/io.h> /* virt_to_phys() */
220 +#include <asm/jz4740.h>
221 +
222 +#include "nanonote_gpm940b0.h"
223 +
224 +#define align2(n) (n)=((((n)+1)>>1)<<1)
225 +#define align4(n) (n)=((((n)+3)>>2)<<2)
226 +#define align8(n) (n)=((((n)+7)>>3)<<3)
227 +
228 +struct jzfb_info {
229 + unsigned int cfg; /* panel mode and pin usage etc. */
230 + unsigned int w;
231 + unsigned int h;
232 + unsigned int bpp; /* bit per pixel */
233 + unsigned int fclk; /* frame clk */
234 + unsigned int hsw; /* hsync width, in pclk */
235 + unsigned int vsw; /* vsync width, in line count */
236 + unsigned int elw; /* end of line, in pclk */
237 + unsigned int blw; /* begin of line, in pclk */
238 + unsigned int efw; /* end of frame, in line count */
239 + unsigned int bfw; /* begin of frame, in line count */
240 +};
241 +
242 +static struct jzfb_info jzfb = {
243 + MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
244 + 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
245 +};
246 +
247 +vidinfo_t panel_info = {
248 + 320, 240, LCD_BPP,
249 +};
250 +
251 +void *lcd_base;
252 +void *lcd_console_address;
253 +int lcd_line_length;
254 +int lcd_color_fg;
255 +int lcd_color_bg;
256 +short console_col;
257 +short console_row;
258 +
259 +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
260 +{
261 + u_long palette_mem_size;
262 + struct jz_fb_info *fbi = &vid->jz_fb;
263 + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
264 +
265 + fbi->screen = (u_long)lcdbase;
266 + fbi->palette_size = 256;
267 + palette_mem_size = fbi->palette_size * sizeof(u16);
268 +
269 + debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
270 + /* locate palette and descs at end of page following fb */
271 + fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
272 +
273 + return 0;
274 +}
275 +
276 +static void jz_lcd_desc_init(vidinfo_t *vid)
277 +{
278 + struct jz_fb_info * fbi;
279 + fbi = &vid->jz_fb;
280 + fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
281 + fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
282 + fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
283 +
284 + #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
285 +
286 + /* populate descriptors */
287 + fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
288 + fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
289 + fbi->dmadesc_fblow->fidr = 0;
290 + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
291 +
292 + fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
293 +
294 + fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
295 + fbi->dmadesc_fbhigh->fidr = 0;
296 + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
297 +
298 + fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
299 + fbi->dmadesc_palette->fidr = 0;
300 + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
301 +
302 + if(NBITS(vid->vl_bpix) < 12) {
303 + /* assume any mode with <12 bpp is palette driven */
304 + fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
305 + fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
306 + /* flips back and forth between pal and fbhigh */
307 + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
308 + } else {
309 + /* palette shouldn't be loaded in true-color mode */
310 + fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
311 + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
312 + }
313 +}
314 +
315 +static int jz_lcd_hw_init(vidinfo_t *vid)
316 +{
317 + struct jz_fb_info *fbi = &vid->jz_fb;
318 + unsigned int val = 0;
319 + unsigned int pclk;
320 + unsigned int stnH;
321 + int pll_div;
322 +
323 + /* Setting Control register */
324 + switch (jzfb.bpp) {
325 + case 1:
326 + val |= LCD_CTRL_BPP_1;
327 + break;
328 + case 2:
329 + val |= LCD_CTRL_BPP_2;
330 + break;
331 + case 4:
332 + val |= LCD_CTRL_BPP_4;
333 + break;
334 + case 8:
335 + val |= LCD_CTRL_BPP_8;
336 + break;
337 + case 15:
338 + val |= LCD_CTRL_RGB555;
339 + case 16:
340 + val |= LCD_CTRL_BPP_16;
341 + break;
342 + case 17 ... 32:
343 + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
344 + break;
345 +
346 + default:
347 + printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
348 + val |= LCD_CTRL_BPP_16;
349 + break;
350 + }
351 +
352 + switch (jzfb.cfg & MODE_MASK) {
353 + case MODE_STN_MONO_DUAL:
354 + case MODE_STN_COLOR_DUAL:
355 + case MODE_STN_MONO_SINGLE:
356 + case MODE_STN_COLOR_SINGLE:
357 + switch (jzfb.bpp) {
358 + case 1:
359 + /* val |= LCD_CTRL_PEDN; */
360 + case 2:
361 + val |= LCD_CTRL_FRC_2;
362 + break;
363 + case 4:
364 + val |= LCD_CTRL_FRC_4;
365 + break;
366 + case 8:
367 + default:
368 + val |= LCD_CTRL_FRC_16;
369 + break;
370 + }
371 + break;
372 + }
373 +
374 + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
375 + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
376 +
377 + switch (jzfb.cfg & MODE_MASK) {
378 + case MODE_STN_MONO_DUAL:
379 + case MODE_STN_COLOR_DUAL:
380 + case MODE_STN_MONO_SINGLE:
381 + case MODE_STN_COLOR_SINGLE:
382 + switch (jzfb.cfg & STN_DAT_PINMASK) {
383 + case STN_DAT_PIN1:
384 + /* Do not adjust the hori-param value. */
385 + break;
386 + case STN_DAT_PIN2:
387 + align2(jzfb.hsw);
388 + align2(jzfb.elw);
389 + align2(jzfb.blw);
390 + break;
391 + case STN_DAT_PIN4:
392 + align4(jzfb.hsw);
393 + align4(jzfb.elw);
394 + align4(jzfb.blw);
395 + break;
396 + case STN_DAT_PIN8:
397 + align8(jzfb.hsw);
398 + align8(jzfb.elw);
399 + align8(jzfb.blw);
400 + break;
401 + }
402 + break;
403 + }
404 +
405 + REG_LCD_CTRL = val;
406 +
407 + switch (jzfb.cfg & MODE_MASK) {
408 + case MODE_STN_MONO_DUAL:
409 + case MODE_STN_COLOR_DUAL:
410 + case MODE_STN_MONO_SINGLE:
411 + case MODE_STN_COLOR_SINGLE:
412 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
413 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
414 + stnH = jzfb.h >> 1;
415 + else
416 + stnH = jzfb.h;
417 +
418 + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
419 + REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
420 +
421 + /* Screen setting */
422 + REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
423 + REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
424 + REG_LCD_DAV = (0 << 16) | (stnH);
425 +
426 + /* AC BIAs signal */
427 + REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
428 +
429 + break;
430 +
431 + case MODE_TFT_GEN:
432 + case MODE_TFT_SHARP:
433 + case MODE_TFT_CASIO:
434 + case MODE_TFT_SAMSUNG:
435 + case MODE_8BIT_SERIAL_TFT:
436 + case MODE_TFT_18BIT:
437 + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
438 + REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
439 + REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
440 + REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
441 + REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
442 + | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
443 + break;
444 + }
445 +
446 + switch (jzfb.cfg & MODE_MASK) {
447 + case MODE_TFT_SAMSUNG:
448 + {
449 + unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
450 + unsigned int rev_s, rev_e, inv_s, inv_e;
451 +
452 + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
453 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
454 +
455 + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
456 + tp_s = jzfb.blw + jzfb.w + 1;
457 + tp_e = tp_s + 1;
458 + ckv_s = tp_s - pclk/(1000000000/4100);
459 + ckv_e = tp_s + total;
460 + rev_s = tp_s - 11; /* -11.5 clk */
461 + rev_e = rev_s + total;
462 + inv_s = tp_s;
463 + inv_e = inv_s + total;
464 + REG_LCD_CLS = (tp_s << 16) | tp_e;
465 + REG_LCD_PS = (ckv_s << 16) | ckv_e;
466 + REG_LCD_SPL = (rev_s << 16) | rev_e;
467 + REG_LCD_REV = (inv_s << 16) | inv_e;
468 + jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
469 + break;
470 + }
471 + case MODE_TFT_SHARP:
472 + {
473 + unsigned int total, cls_s, cls_e, ps_s, ps_e;
474 + unsigned int spl_s, spl_e, rev_s, rev_e;
475 + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
476 + spl_s = 1;
477 + spl_e = spl_s + 1;
478 + cls_s = 0;
479 + cls_e = total - 60; /* > 4us (pclk = 80ns) */
480 + ps_s = cls_s;
481 + ps_e = cls_e;
482 + rev_s = total - 40; /* > 3us (pclk = 80ns) */
483 + rev_e = rev_s + total;
484 + jzfb.cfg |= STFT_PSHI;
485 + REG_LCD_SPL = (spl_s << 16) | spl_e;
486 + REG_LCD_CLS = (cls_s << 16) | cls_e;
487 + REG_LCD_PS = (ps_s << 16) | ps_e;
488 + REG_LCD_REV = (rev_s << 16) | rev_e;
489 + break;
490 + }
491 + case MODE_TFT_CASIO:
492 + break;
493 + }
494 +
495 + /* Configure the LCD panel */
496 + REG_LCD_CFG = jzfb.cfg;
497 +
498 + /* Timing setting */
499 + __cpm_stop_lcd();
500 +
501 + val = jzfb.fclk; /* frame clk */
502 + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
503 + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
504 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
505 + } else {
506 + /* serial mode: Hsync period = 3*Width_Pixel */
507 + pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
508 + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
509 + }
510 +
511 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
512 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
513 + pclk = (pclk * 3);
514 +
515 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
516 + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
517 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
518 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
519 + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
520 +
521 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
522 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
523 + pclk >>= 1;
524 +
525 + pll_div = (REG_CPM_CPCCR & CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
526 + pll_div = pll_div ? 1 : 2;
527 + val = (__cpm_get_pllout() / pll_div) / pclk;
528 + val--;
529 + if (val > 0x1ff) {
530 + printf("CPM_LPCDR too large, set it to 0x1ff\n");
531 + val = 0x1ff;
532 + }
533 + __cpm_set_pixdiv(val);
534 +
535 + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
536 + if (val > 150000000) {
537 + printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
538 + printf("Change LCDClock to 150MHz\n");
539 + val = 150000000;
540 + }
541 + val = (__cpm_get_pllout() / pll_div) / val;
542 + val--;
543 + if (val > 0x1f) {
544 + printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
545 + val = 0x1f;
546 + }
547 + __cpm_set_ldiv( val );
548 + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
549 +
550 + __cpm_start_lcd();
551 + udelay(1000);
552 +
553 + REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
554 +
555 + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
556 + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
557 + REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
558 +
559 + return 0;
560 +}
561 +
562 +void lcd_ctrl_init (void *lcdbase)
563 +{
564 + __lcd_display_pin_init();
565 + __lcd_display_on() ;
566 +
567 + jz_lcd_init_mem(lcdbase, &panel_info);
568 + jz_lcd_desc_init(&panel_info);
569 + jz_lcd_hw_init(&panel_info);
570 +
571 +}
572 +
573 +/*
574 + * Before enabled lcd controller, lcd registers should be configured correctly.
575 + */
576 +void lcd_enable (void)
577 +{
578 + REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
579 + REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
580 +}
581 +
582 +void lcd_disable (void)
583 +{
584 + REG_LCD_CTRL |= (1<<4);
585 +}
586 +
587 +void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
588 +{
589 +}
590 +
591 +void lcd_initcolregs (void)
592 +{
593 +}
594 diff --git a/drivers/video/nanonote_gpm940b0.h b/drivers/video/nanonote_gpm940b0.h
595 new file mode 100644
596 index 0000000..efe491e
597 --- /dev/null
598 +++ b/drivers/video/nanonote_gpm940b0.h
599 @@ -0,0 +1,135 @@
600 +/*
601 + * JzRISC lcd controller
602 + *
603 + * Xiangfu Liu <xiangfu@sharism.cc>
604 + *
605 + * This program is free software; you can redistribute it and/or
606 + * modify it under the terms of the GNU General Public License as
607 + * published by the Free Software Foundation; either version 2 of
608 + * the License, or (at your option) any later version.
609 + *
610 + * This program is distributed in the hope that it will be useful,
611 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
612 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
613 + * GNU General Public License for more details.
614 + *
615 + * You should have received a copy of the GNU General Public License
616 + * along with this program; if not, write to the Free Software
617 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
618 + * MA 02111-1307 USA
619 + */
620 +
621 +#ifndef __QI_LB60_GPM940B0_H__
622 +#define __QI_LB60_GPM940B0_H__
623 +
624 +struct lcd_desc{
625 + unsigned int next_desc; /* LCDDAx */
626 + unsigned int databuf; /* LCDSAx */
627 + unsigned int frame_id; /* LCDFIDx */
628 + unsigned int cmd; /* LCDCMDx */
629 +};
630 +
631 +#define MODE_MASK 0x0f
632 +#define MODE_TFT_GEN 0x00
633 +#define MODE_TFT_SHARP 0x01
634 +#define MODE_TFT_CASIO 0x02
635 +#define MODE_TFT_SAMSUNG 0x03
636 +#define MODE_CCIR656_NONINT 0x04
637 +#define MODE_CCIR656_INT 0x05
638 +#define MODE_STN_COLOR_SINGLE 0x08
639 +#define MODE_STN_MONO_SINGLE 0x09
640 +#define MODE_STN_COLOR_DUAL 0x0a
641 +#define MODE_STN_MONO_DUAL 0x0b
642 +#define MODE_8BIT_SERIAL_TFT 0x0c
643 +
644 +#define MODE_TFT_18BIT (1<<7)
645 +
646 +#define STN_DAT_PIN1 (0x00 << 4)
647 +#define STN_DAT_PIN2 (0x01 << 4)
648 +#define STN_DAT_PIN4 (0x02 << 4)
649 +#define STN_DAT_PIN8 (0x03 << 4)
650 +#define STN_DAT_PINMASK STN_DAT_PIN8
651 +
652 +#define STFT_PSHI (1 << 15)
653 +#define STFT_CLSHI (1 << 14)
654 +#define STFT_SPLHI (1 << 13)
655 +#define STFT_REVHI (1 << 12)
656 +
657 +#define SYNC_MASTER (0 << 16)
658 +#define SYNC_SLAVE (1 << 16)
659 +
660 +#define DE_P (0 << 9)
661 +#define DE_N (1 << 9)
662 +
663 +#define PCLK_P (0 << 10)
664 +#define PCLK_N (1 << 10)
665 +
666 +#define HSYNC_P (0 << 11)
667 +#define HSYNC_N (1 << 11)
668 +
669 +#define VSYNC_P (0 << 8)
670 +#define VSYNC_N (1 << 8)
671 +
672 +#define DATA_NORMAL (0 << 17)
673 +#define DATA_INVERSE (1 << 17)
674 +
675 +
676 +/* Jz LCDFB supported I/O controls. */
677 +#define FBIOSETBACKLIGHT 0x4688
678 +#define FBIODISPON 0x4689
679 +#define FBIODISPOFF 0x468a
680 +#define FBIORESET 0x468b
681 +#define FBIOPRINT_REG 0x468c
682 +
683 +/*
684 + * LCD panel specific definition
685 + */
686 +#define MODE (0xc9) /* 8bit serial RGB */
687 +
688 +#define __spi_write_reg1(reg, val) \
689 +do { \
690 + unsigned char no; \
691 + unsigned short value; \
692 + unsigned char a=reg; \
693 + unsigned char b=val; \
694 + __gpio_set_pin(SPEN); \
695 + __gpio_set_pin(SPCK); \
696 + __gpio_clear_pin(SPDA); \
697 + __gpio_clear_pin(SPEN); \
698 + value=((a<<8)|(b&0xFF)); \
699 + for(no=0;no<16;no++) \
700 + { \
701 + __gpio_clear_pin(SPCK); \
702 + if((value&0x8000)==0x8000) \
703 + __gpio_set_pin(SPDA); \
704 + else \
705 + __gpio_clear_pin(SPDA); \
706 + __gpio_set_pin(SPCK); \
707 + value=(value<<1); \
708 + } \
709 + __gpio_set_pin(SPEN); \
710 +} while (0)
711 +
712 +#define __lcd_display_pin_init() \
713 +do { \
714 + __cpm_start_tcu(); \
715 + __gpio_as_output(SPEN); /* use SPDA */ \
716 + __gpio_as_output(SPCK); /* use SPCK */ \
717 + __gpio_as_output(SPDA); /* use SPDA */ \
718 +} while (0)
719 +
720 +#define __lcd_display_on() \
721 +do { \
722 + __spi_write_reg1(0x05, 0x1e); \
723 + __spi_write_reg1(0x05, 0x5e); \
724 + __spi_write_reg1(0x07, 0x8d); \
725 + __spi_write_reg1(0x13, 0x01); \
726 + __spi_write_reg1(0x05, 0x5f); \
727 +} while (0)
728 +
729 +#define __lcd_display_off() \
730 +do { \
731 + __spi_write_reg1(0x05, 0x5e); \
732 +} while (0)
733 +
734 +#endif /* __QI_LB60_GPM940B0_H__ */
735 diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
736 index 52b370c..d3e78ad 100644
737 --- a/include/configs/qi_lb60.h
738 +++ b/include/configs/qi_lb60.h
739 @@ -32,6 +32,13 @@
740 * Miscellaneous configurable options
741 */
742 #define CONFIG_NANONOTE
743 +
744 +#define CONFIG_LCD
745 +#define CONFIG_SYS_WHITE_ON_BLACK
746 +#define LCD_BPP LCD_COLOR32
747 +#define CONFIG_VIDEO_GPM940B0
748 +
749 +
750 #define CONFIG_JZ4740_MMC
751 #define CONFIG_MMC 1
752 #define CONFIG_FAT 1
753 diff --git a/include/lcd.h b/include/lcd.h
754 index 42070d7..6de5482 100644
755 --- a/include/lcd.h
756 +++ b/include/lcd.h
757 @@ -263,8 +263,44 @@ typedef struct vidinfo {
758
759 void init_panel_info(vidinfo_t *vid);
760
761 -#else
762 +#elif defined(CONFIG_JZSOC)
763 +/*
764 + * LCD controller stucture for JZSOC: JZ4740
765 + */
766 +struct jz_fb_dma_descriptor {
767 + u_long fdadr; /* Frame descriptor address register */
768 + u_long fsadr; /* Frame source address register */
769 + u_long fidr; /* Frame ID register */
770 + u_long ldcmd; /* Command register */
771 +};
772 +
773 +/*
774 + * Jz LCD info
775 + */
776 +struct jz_fb_info {
777 +
778 + u_long fdadr0; /* physical address of frame/palette descriptor */
779 + u_long fdadr1; /* physical address of frame descriptor */
780 +
781 + /* DMA descriptors */
782 + struct jz_fb_dma_descriptor * dmadesc_fblow;
783 + struct jz_fb_dma_descriptor * dmadesc_fbhigh;
784 + struct jz_fb_dma_descriptor * dmadesc_palette;
785 + u_long screen; /* address of frame buffer */
786 + u_long palette; /* address of palette memory */
787 + u_int palette_size;
788 +};
789 +typedef struct vidinfo {
790 + ushort vl_col; /* Number of columns (i.e. 640) */
791 + ushort vl_row; /* Number of rows (i.e. 480) */
792 + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
793 +
794 + struct jz_fb_info jz_fb;
795 +} vidinfo_t;
796 +
797 +extern vidinfo_t panel_info;
798
799 +#else
800 typedef struct vidinfo {
801 ushort vl_col; /* Number of columns (i.e. 160) */
802 ushort vl_row; /* Number of rows (i.e. 100) */
803 @@ -318,6 +354,7 @@ void lcd_show_board_info(void);
804 #define LCD_COLOR4 2
805 #define LCD_COLOR8 3
806 #define LCD_COLOR16 4
807 +#define LCD_COLOR32 5
808
809 /*----------------------------------------------------------------------*/
810 #if defined(CONFIG_LCD_INFO_BELOW_LOGO)
811 @@ -369,7 +406,7 @@ void lcd_show_board_info(void);
812 # define CONSOLE_COLOR_GREY 14
813 # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
814
815 -#else
816 +#elif LCD_BPP == LCD_COLOR16
817
818 /*
819 * 16bpp color definitions
820 @@ -377,6 +414,15 @@ void lcd_show_board_info(void);
821 # define CONSOLE_COLOR_BLACK 0x0000
822 # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
823
824 +#elif LCD_BPP == LCD_COLOR32
825 +/*
826 + * 18,24,32 bpp color definitions
827 + */
828 +# define CONSOLE_COLOR_BLACK 0x00000000
829 +# define CONSOLE_COLOR_WHITE 0xffffffff /* Must remain last / highest */
830 +
831 +#else
832 +
833 #endif /* color definitions */
834
835 /************************************************************************/
836 @@ -406,7 +452,7 @@ void lcd_show_board_info(void);
837 #if LCD_BPP == LCD_MONOCHROME
838 # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
839 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
840 -#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
841 +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR32)
842 # define COLOR_MASK(c) (c)
843 #else
844 # error Unsupported LCD BPP.
845 --
846 1.7.9.5
847
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