package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_amazon_se.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <asm/delay.h>
  44
  45 /*
  46  *  Chip Specific Head File
  47  */
  48 #include "ifxmips_atm_core.h"
  49 #include "ifxmips_atm_fw_amazon_se.h"
  50
  51 #include <lantiq_soc.h>
  52
  53
  54 /*
  55  * ####################################
  56  *              Definition
  57  * ####################################
  58  */
  59
  60 /*
  61  *  EMA Settings
  62  */
  63 #define EMA_CMD_BUF_LEN      0x0040
  64 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
  65 #define EMA_DATA_BUF_LEN     0x0100
  66 #define EMA_DATA_BASE_ADDR   (0x00000B00 << 2)
  67 #define EMA_WRITE_BURST      0x2
  68 #define EMA_READ_BURST       0x2
  69
  70
  71
  72 /*
  73  * ####################################
  74  *             Declaration
  75  * ####################################
  76  */
  77
  78 /*
  79  *  Hardware Init/Uninit Functions
  80  */
  81 static inline void init_pmu(void);
  82 static inline void uninit_pmu(void);
  83 static inline void reset_ppe(void);
  84 static inline void init_ema(void);
  85 static inline void init_mailbox(void);
  86 static inline void init_atm_tc(void);
  87 static inline void clear_share_buffer(void);
  88
  89
  90
  91 /*
  92  * ####################################
  93  *            Local Variable
  94  * ####################################
  95  */
  96
  97
  98
  99 /*
 100  * ####################################
 101  *            Local Function
 102  * ####################################
 103  */
 104 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
 105 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
 106 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
 107 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
 108 #define IFX_PMU_MODULE_TPE       BIT(13)
 109 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
 110
 111 static inline void init_pmu(void)
 112 {
 113     //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
 114     //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
 115 /*    PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
 116     PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
 117     PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
 118     //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
 119     PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
 120     DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
 121         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
 122                 IFX_PMU_MODULE_PPE_TC |
 123                 IFX_PMU_MODULE_PPE_EMA |
 124                 IFX_PMU_MODULE_TPE |
 125                 IFX_PMU_MODULE_DSL_DFE);
 126 }
 127
 128 static inline void uninit_pmu(void)
 129 {
 130     /*PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
 131     PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
 132     PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
 133     //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
 134     PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
 135     DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
 136     //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/
 137 }
 138
 139 static inline void reset_ppe(void)
 140 {
 141 #if 0 //MODULE
 142     unsigned int etop_cfg;
 143     unsigned int etop_mdio_cfg;
 144     unsigned int etop_ig_plen_ctrl;
 145     unsigned int enet_mac_cfg;
 146
 147     etop_cfg            = *IFX_PP32_ETOP_CFG;
 148     etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;
 149     etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;
 150     enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;
 151
 152     *IFX_PP32_ETOP_CFG  = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;
 153
 154     //  reset PPE
 155     ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
 156
 157     *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;
 158     *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
 159     *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;
 160     *IFX_PP32_ETOP_CFG          = etop_cfg;
 161 #endif
 162 }
 163
 164 static inline void init_ema(void)
 165 {
 166     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 167     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 168     IFX_REG_W32(0x000000FF, EMA_IER);
 169     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 170 }
 171
 172 static inline void init_mailbox(void)
 173 {
 174     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 175     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 176     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 177     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 178 }
 179
 180 static inline void init_atm_tc(void)
 181 {
 182     IFX_REG_W32(0x0000,     DREG_AT_CTRL);
 183     IFX_REG_W32(0x0000,     DREG_AR_CTRL);
 184     IFX_REG_W32(0x0,        DREG_AT_IDLE0);
 185     IFX_REG_W32(0x0,        DREG_AT_IDLE1);
 186     IFX_REG_W32(0x0,        DREG_AR_IDLE0);
 187     IFX_REG_W32(0x0,        DREG_AR_IDLE1);
 188     IFX_REG_W32(0x40,       RFBI_CFG);
 189     IFX_REG_W32(0x0700,     SFSM_DBA0);
 190     IFX_REG_W32(0x0818,     SFSM_DBA1);
 191     IFX_REG_W32(0x0930,     SFSM_CBA0);
 192     IFX_REG_W32(0x0944,     SFSM_CBA1);
 193     IFX_REG_W32(0x14014,    SFSM_CFG0);
 194     IFX_REG_W32(0x14014,    SFSM_CFG1);
 195     IFX_REG_W32(0x0958,     FFSM_DBA0);
 196     IFX_REG_W32(0x09AC,     FFSM_DBA1);
 197     IFX_REG_W32(0x10006,    FFSM_CFG0);
 198     IFX_REG_W32(0x10006,    FFSM_CFG1);
 199     IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
 200     IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
 201 }
 202
 203 static inline void clear_share_buffer(void)
 204 {
 205     volatile u32 *p = SB_RAM0_ADDR(0);
 206     unsigned int i;
 207
 208     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )
 209         IFX_REG_W32(0, p++);
 210 }
 211
 212 /*
 213  *  Description:
 214  *    Download PPE firmware binary code.
 215  *  Input:
 216  *    src       --- u32 *, binary code buffer
 217  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 218  *  Output:
 219  *    int       --- 0:    Success
 220  *                  else:           Error Code
 221  */
 222 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 223 {
 224     volatile u32 *dest;
 225
 226     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 227         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 228         return -1;
 229
 230     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 231         IFX_REG_W32(0x00, CDM_CFG);
 232     else
 233         IFX_REG_W32(0x04, CDM_CFG);
 234
 235     /*  copy code   */
 236     dest = CDM_CODE_MEMORY(0, 0);
 237     while ( code_dword_len-- > 0 )
 238         IFX_REG_W32(*code_src++, dest++);
 239
 240     /*  copy data   */
 241     dest = CDM_DATA_MEMORY(0, 0);
 242     while ( data_dword_len-- > 0 )
 243         IFX_REG_W32(*data_src++, dest++);
 244
 245     return 0;
 246 }
 247
 248
 249
 250 /*
 251  * ####################################
 252  *           Global Function
 253  * ####################################
 254  */
 255
 256 extern void ase_fw_ver(unsigned int *major, unsigned int *minor)
 257 {
 258     ASSERT(major != NULL, "pointer is NULL");
 259     ASSERT(minor != NULL, "pointer is NULL");
 260
 261     *major = FW_VER_ID->major;
 262     *minor = FW_VER_ID->minor;
 263 }
 264
 265 void ase_init(void)
 266 {
 267     init_pmu();
 268
 269     reset_ppe();
 270
 271     init_ema();
 272
 273     init_mailbox();
 274
 275     init_atm_tc();
 276
 277     clear_share_buffer();
 278 }
 279
 280 void ase_shutdown(void)
 281 {
 282     uninit_pmu();
 283 }
 284
 285 /*
 286  *  Description:
 287  *    Initialize and start up PP32.
 288  *  Input:
 289  *    none
 290  *  Output:
 291  *    int  --- 0: Success
 292  *             else:        Error Code
 293  */
 294 int ase_start(int pp32)
 295 {
 296     int ret;
 297
 298     /*  download firmware   */
 299     ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 300     if ( ret != 0 )
 301         return ret;
 302
 303     /*  run PP32    */
 304     IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL);
 305
 306     /*  idle for a while to let PP32 init itself    */
 307     udelay(10);
 308
 309     return 0;
 310 }
 311
 312 /*
 313  *  Description:
 314  *    Halt PP32.
 315  *  Input:
 316  *    none
 317  *  Output:
 318  *    none
 319  */
 320 void ase_stop(int pp32)
 321 {
 322     /*  halt PP32   */
 323     IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);
 324 }
 325
 326 struct ltq_atm_ops ase_ops = {
 327         .init = ase_init,
 328         .shutdown = ase_shutdown,
 329         .start = ase_start,
 330         .stop = ase_stop,
 331         .fw_ver = ase_fw_ver,
 332 };
 333