1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_ar9.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
46 * Chip Specific Head File
48 #include "ifxmips_atm_core.h"
50 #include "ifxmips_atm_fw_ar9.h"
51 #include "ifxmips_atm_fw_regs_ar9.h"
53 #include <lantiq_soc.h>
58 * ####################################
60 * ####################################
66 #define EMA_CMD_BUF_LEN 0x0040
67 #define EMA_CMD_BASE_ADDR (0x00003B80 << 2)
68 #define EMA_DATA_BUF_LEN 0x0100
69 #define EMA_DATA_BASE_ADDR (0x00003C00 << 2)
70 #define EMA_WRITE_BURST 0x2
71 #define EMA_READ_BURST 0x2
76 * ####################################
78 * ####################################
82 * Hardware Init/Uninit Functions
84 static inline void init_pmu(void);
85 static inline void uninit_pmu(void);
86 static inline void reset_ppe(void);
87 static inline void init_ema(void);
88 static inline void init_mailbox(void);
89 static inline void clear_share_buffer(void);
94 * ####################################
96 * ####################################
102 * ####################################
104 * ####################################
107 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
108 #define IFX_PMU_MODULE_PPE_TC BIT(21)
109 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
110 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
111 #define IFX_PMU_MODULE_TPE BIT(13)
112 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
114 static inline void init_pmu(void)
116 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01
|
117 IFX_PMU_MODULE_PPE_TC
|
118 IFX_PMU_MODULE_PPE_EMA
|
119 IFX_PMU_MODULE_PPE_QSB
|
121 IFX_PMU_MODULE_DSL_DFE
);
124 static inline void uninit_pmu(void)
128 static inline void reset_ppe(void)
132 // ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
136 static inline void init_ema(void)
138 IFX_REG_W32((EMA_CMD_BUF_LEN
<< 16) | (EMA_CMD_BASE_ADDR
>> 2), EMA_CMDCFG
);
139 IFX_REG_W32((EMA_DATA_BUF_LEN
<< 16) | (EMA_DATA_BASE_ADDR
>> 2), EMA_DATACFG
);
140 IFX_REG_W32(0x000000FF, EMA_IER
);
141 IFX_REG_W32(EMA_READ_BURST
| (EMA_WRITE_BURST
<< 2), EMA_CFG
);
144 static inline void init_mailbox(void)
146 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC
);
147 IFX_REG_W32(0x00000000, MBOX_IGU1_IER
);
148 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC
);
149 IFX_REG_W32(0x00000000, MBOX_IGU3_IER
);
152 static inline void clear_share_buffer(void)
154 volatile u32
*p
= SB_RAM0_ADDR(0);
157 for ( i
= 0; i
< SB_RAM0_DWLEN
+ SB_RAM1_DWLEN
+ SB_RAM2_DWLEN
+ SB_RAM3_DWLEN
+ SB_RAM4_DWLEN
; i
++ )
161 static inline int pp32_download_code(u32
*code_src
, unsigned int code_dword_len
, u32
*data_src
, unsigned int data_dword_len
)
165 if ( code_src
== 0 || ((unsigned long)code_src
& 0x03) != 0
166 || data_src
== 0 || ((unsigned long)data_src
& 0x03) != 0 )
169 if ( code_dword_len
<= CDM_CODE_MEMORYn_DWLEN(0) )
170 IFX_REG_W32(0x00, CDM_CFG
);
172 IFX_REG_W32(0x04, CDM_CFG
);
175 dest
= CDM_CODE_MEMORY(0, 0);
176 while ( code_dword_len
-- > 0 )
177 IFX_REG_W32(*code_src
++, dest
++);
180 dest
= CDM_DATA_MEMORY(0, 0);
181 while ( data_dword_len
-- > 0 )
182 IFX_REG_W32(*data_src
++, dest
++);
187 void ar9_fw_ver(unsigned int *major
, unsigned int *minor
)
189 ASSERT(major
!= NULL
, "pointer is NULL");
190 ASSERT(minor
!= NULL
, "pointer is NULL");
192 *major
= FW_VER_ID
->major
;
193 *minor
= FW_VER_ID
->minor
;
202 clear_share_buffer();
205 void ar9_shutdown(void)
207 ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01
|
208 IFX_PMU_MODULE_PPE_TC
|
209 IFX_PMU_MODULE_PPE_EMA
|
210 IFX_PMU_MODULE_PPE_QSB
|
212 IFX_PMU_MODULE_DSL_DFE
);
215 int ar9_start(int pp32
)
219 ret
= pp32_download_code(ar9_fw_bin
, sizeof(ar9_fw_bin
) / sizeof(*ar9_fw_bin
),
220 ar9_fw_data
, sizeof(ar9_fw_data
) / sizeof(*ar9_fw_data
));
224 IFX_REG_W32(DBG_CTRL_RESTART
, PP32_DBG_CTRL(0));
231 void ar9_stop(int pp32
)
233 IFX_REG_W32(DBG_CTRL_STOP
, PP32_DBG_CTRL(0));
236 struct ltq_atm_ops ar9_ops
= {
238 .shutdown
= ar9_shutdown
,
241 .fw_ver
= ar9_fw_ver
,