1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_fw_regs_common.h
5 ** MODULES : ATM (ADSL)
9 ** DESCRIPTION : ATM Driver (Firmware Register Structures)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 4 AUG 2005 Xu Liang Initiate Version
22 ** 23 OCT 2006 Xu Liang Add GPL header.
23 ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
24 *******************************************************************************/
28 #ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
29 #define IFXMIPS_ATM_FW_REGS_COMMON_H
32 #if defined(CONFIG_DANUBE)
33 #include "ifxmips_atm_fw_regs_danube.h"
34 #elif defined(CONFIG_AMAZON_SE)
35 #include "ifxmips_atm_fw_regs_amazon_se.h"
36 #elif defined(CONFIG_AR9)
37 #include "ifxmips_atm_fw_regs_ar9.h"
38 #elif defined(CONFIG_VR9)
39 #include "ifxmips_atm_fw_regs_vr9.h"
41 #error Platform is not specified!
49 #if defined(__BIG_ENDIAN)
50 struct uni_cell_header
{
58 struct uni_cell_header
{
65 #endif // defined(__BIG_ENDIAN)
68 * Inband Header and Trailer
70 #if defined(__BIG_ENDIAN)
71 struct rx_inband_trailer
{
75 unsigned int stw_res1
:4;
76 unsigned int stw_clp
:1;
77 unsigned int stw_ec
:1;
78 unsigned int stw_uu
:1;
79 unsigned int stw_cpi
:1;
80 unsigned int stw_ovz
:1;
81 unsigned int stw_mfl
:1;
82 unsigned int stw_usz
:1;
83 unsigned int stw_crc
:1;
84 unsigned int stw_il
:1;
85 unsigned int stw_ra
:1;
86 unsigned int stw_res2
:2;
95 struct tx_inband_header
{
106 unsigned int res1
:8;
109 struct rx_inband_trailer
{
111 unsigned int stw_res2
:2;
112 unsigned int stw_ra
:1;
113 unsigned int stw_il
:1;
114 unsigned int stw_crc
:1;
115 unsigned int stw_usz
:1;
116 unsigned int stw_mfl
:1;
117 unsigned int stw_ovz
:1;
118 unsigned int stw_cpi
:1;
119 unsigned int stw_uu
:1;
120 unsigned int stw_ec
:1;
121 unsigned int stw_clp
:1;
122 unsigned int stw_res1
:4;
128 unsigned int vci
:16;
133 struct tx_inband_header
{
137 unsigned int vci
:16;
141 unsigned int res1
:8;
146 #endif // defined(__BIG_ENDIAN)
149 * MIB Table Maintained by Firmware
151 struct wan_mib_table
{
153 u32 wrx_drophtu_cell
;
157 u32 wrx_dropdes_cell
;
158 u32 wrx_correct_cell
;
168 * Host-PPE Communication Data Structure
171 #if defined(__BIG_ENDIAN)
173 unsigned int family
:4;
174 unsigned int fwtype
:4;
175 unsigned int interface
:4;
176 unsigned int fwmode
:4;
177 unsigned int major
:8;
178 unsigned int minor
:8;
181 struct wrx_queue_config
{
183 unsigned int res2
:27;
184 unsigned int dmach
:4;
185 unsigned int errdp
:1;
187 unsigned int oversize
:16;
188 unsigned int undersize
:16;
190 unsigned int res1
:16;
191 unsigned int mfs
:16;
193 unsigned int uumask
:8;
194 unsigned int cpimask
:8;
195 unsigned int uuexp
:8;
196 unsigned int cpiexp
:8;
199 struct wrx_queue_context
{
201 unsigned int curr_len
:16;
202 unsigned int res0
:12;
205 unsigned int clp1
:1;
206 unsigned int aal5dp
:1;
212 unsigned int curr_des0
;
213 unsigned int curr_des1
;
216 unsigned int res1
[11];
218 unsigned int last_dword
;
221 struct wtx_port_config
{
222 unsigned int res1
:27;
224 unsigned int qsben
:1;
227 struct wtx_queue_config
{
228 unsigned int res1
:16;
229 unsigned int same_vc_qmap
:8;
230 unsigned int res2
:1;
231 unsigned int sbid
:1;
232 unsigned int qsb_vcid
:4; // Which QSB queue (VCID) does this TX queue map to.
233 unsigned int res3
:1;
234 unsigned int qsben
:1;
237 struct wrx_desc_context
{
238 unsigned int dmach_wrptr
: 16;
239 unsigned int dmach_rdptr
: 16;
241 unsigned int res0
: 16;
242 unsigned int dmach_fcnt
: 16;
244 unsigned int res1
: 11;
245 unsigned int desbuf_wrptr
: 5;
246 unsigned int res2
: 11;
247 unsigned int desbuf_rdptr
: 5;
249 unsigned int res3
: 27;
250 unsigned int desbuf_vcnt
: 5;
253 struct wrx_dma_channel_config
{
255 unsigned int res1
:1;
256 unsigned int mode
:2;
257 unsigned int rlcfg
:1;
258 unsigned int desba
:28;
260 unsigned int chrl
:16;
261 unsigned int clp1th
:16;
263 unsigned int deslen
:16;
264 unsigned int vlddes
:16;
267 struct wtx_dma_channel_config
{
269 unsigned int res2
:1;
270 unsigned int mode
:2;
271 unsigned int res3
:1;
272 unsigned int desba
:28;
274 unsigned int res1
:32;
276 unsigned int deslen
:16;
277 unsigned int vlddes
:16;
281 unsigned int res1
:1;
285 unsigned int vci
:16;
293 unsigned int pid_mask
:2;
294 unsigned int vpi_mask
:8;
295 unsigned int vci_mask
:16;
296 unsigned int pti_mask
:3;
297 unsigned int clear
:1;
301 unsigned int res1
:12;
302 unsigned int cellid
:4;
303 unsigned int res2
:5;
304 unsigned int type
:1;
306 unsigned int res3
:5;
310 struct rx_descriptor
{
316 unsigned int res1
:3;
317 unsigned int byteoff
:2;
318 unsigned int res2
:2;
321 unsigned int datalen
:16;
323 unsigned int res3
:4;
324 unsigned int dataptr
:28;
327 struct tx_descriptor
{
333 unsigned int byteoff
:5;
334 unsigned int res1
:5;
335 unsigned int iscell
:1;
337 unsigned int datalen
:16;
339 unsigned int res2
:4;
340 unsigned int dataptr
:28;
343 struct wrx_queue_config
{
345 unsigned int errdp
:1;
346 unsigned int dmach
:4;
347 unsigned int res2
:27;
349 unsigned int undersize
:16;
350 unsigned int oversize
:16;
352 unsigned int mfs
:16;
353 unsigned int res1
:16;
355 unsigned int cpiexp
:8;
356 unsigned int uuexp
:8;
357 unsigned int cpimask
:8;
358 unsigned int uumask
:8;
361 struct wtx_port_config
{
362 unsigned int qsben
:1;
364 unsigned int res1
:27;
367 struct wtx_queue_config
{
368 unsigned int qsben
:1;
369 unsigned int res3
:1;
370 unsigned int qsb_vcid
:4; // Which QSB queue (VCID) does this TX queue map to.
371 unsigned int sbid
:1;
372 unsigned int res2
:1;
373 unsigned int same_vc_qmap
:8;
374 unsigned int res1
:16;
377 struct wrx_dma_channel_config
380 unsigned int desba
:28;
381 unsigned int rlcfg
:1;
382 unsigned int mode
:2;
383 unsigned int res1
:1;
385 unsigned int clp1th
:16;
386 unsigned int chrl
:16;
388 unsigned int vlddes
:16;
389 unsigned int deslen
:16;
392 struct wtx_dma_channel_config
{
394 unsigned int desba
:28;
395 unsigned int res3
:1;
396 unsigned int mode
:2;
397 unsigned int res2
:1;
399 unsigned int res1
:32;
401 unsigned int vlddes
:16;
402 unsigned int deslen
:16;
405 struct rx_descriptor
{
407 unsigned int dataptr
:28;
408 unsigned int res3
:4;
410 unsigned int datalen
:16;
413 unsigned int res2
:2;
414 unsigned int byteoff
:2;
415 unsigned int res1
:3;
422 struct tx_descriptor
{
424 unsigned int dataptr
:28;
425 unsigned int res2
:4;
427 unsigned int datalen
:16;
429 unsigned int iscell
:1;
430 unsigned int res1
:5;
431 unsigned int byteoff
:5;
437 #endif // defined(__BIG_ENDIAN)
439 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
440 #if defined(__BIG_ENDIAN)
442 struct Retx_adsl_ppe_intf
{
443 unsigned int res0_0
: 16;
444 unsigned int dtu_sid
: 8;
445 unsigned int dtu_timestamp
: 8;
447 unsigned int res1_0
: 16;
448 unsigned int local_time
: 8;
449 unsigned int res1_1
: 5;
450 unsigned int is_last_cw
: 1;
451 unsigned int reinit_flag
: 1;
452 unsigned int is_bad_cw
: 1;
455 struct Retx_adsl_ppe_intf_rec
{
457 unsigned int local_time
: 8;
458 unsigned int res1_1
: 5;
459 unsigned int is_last_cw
: 1;
460 unsigned int reinit_flag
: 1;
461 unsigned int is_bad_cw
: 1;
463 unsigned int dtu_sid
: 8;
464 unsigned int dtu_timestamp
: 8;
468 struct Retx_mode_cfg
{
469 unsigned int res0
:8;
470 unsigned int invld_range
:8; // used for rejecting the too late arrival of the retransmitted DTU
471 unsigned int buff_size
:8; // the total number of cells in playout buffer is 32 * buff_size
472 unsigned int res1
:7;
473 unsigned int retx_en
:1;
476 struct Retx_Tsync_cfg
{
477 unsigned int fw_alpha
:16; // number of consecutive HEC error cell causes that the cell delineation state machine transit from SYNC to HUNT (0 means never)
478 unsigned int sync_inp
:16; // reserved
482 unsigned int res0
:8;
483 unsigned int td_max
:8; // maximum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
484 unsigned int res1
:8;
485 unsigned int td_min
:8; // minimum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
488 struct Retx_MIB_Timer_cfg
{
489 unsigned int ticks_per_sec
: 16;
490 unsigned int tick_cycle
: 16;
493 struct DTU_stat_info
{
494 unsigned int complete
: 1;
495 unsigned int bad
: 1;
496 unsigned int res0_0
: 14;
497 unsigned int time_stamp
: 8;
498 unsigned int cell_cnt
: 8;
500 unsigned int dtu_rd_ptr
: 16;
501 unsigned int dtu_wr_ptr
: 16;
504 struct Retx_ctrl_field
{
505 unsigned int res0
: 1;
507 unsigned int l2_drop
: 1;
508 unsigned int res1
: 13;
509 unsigned int retx
: 1;
511 unsigned int dtu_sid
: 8;
512 unsigned int cell_sid
: 8;
516 #error Little Endian is not supported yet.
520 unsigned int update_flag
; // 00
521 unsigned int res0
; // 04
522 unsigned int MinDelayrt
; // 08
523 unsigned int MaxDelayrt
; // 0C
524 unsigned int res1
; // 10
525 unsigned int res2
; // 14
526 unsigned int RetxEnable
; // 18
527 unsigned int ServiceSpecificReTx
; // 1C
528 unsigned int res3
; // 20
529 unsigned int ReTxPVC
; // 24
530 unsigned int res4
; // 28
531 unsigned int res5
; // 2C
532 unsigned int res6
; // 30
533 unsigned int res7
; // 34
534 unsigned int res8
; // 38
535 unsigned int res9
; // 3C
536 unsigned int res10
; // 40
537 unsigned int res11
; // 44
538 unsigned int res12
; // 48
539 unsigned int res13
; // 4C
540 unsigned int RxDtuCorruptedCNT
; // 50
541 unsigned int RxRetxDtuUnCorrectedCNT
;// 54
542 unsigned int RxLastEFB
; // 58
543 unsigned int RxDtuCorrectedCNT
; // 5C
549 #endif // IFXMIPS_ATM_FW_REGS_COMMON_H