1 /******************************************************************************
3 ** FILE NAME : ifxmips_ptm_danube.c
9 ** DESCRIPTION : PTM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <linux/platform_device.h>
44 #include <linux/reset.h>
45 #include <linux/delay.h>
48 * Chip Specific Head File
50 #include "ifxmips_ptm_adsl.h"
51 #include "ifxmips_ptm_fw_danube.h"
53 #include <lantiq_soc.h>
56 * ####################################
58 * ####################################
64 #define EMA_CMD_BUF_LEN 0x0040
65 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
66 #define EMA_DATA_BUF_LEN 0x0100
67 #define EMA_DATA_BASE_ADDR (0x00000B00 << 2)
68 #define EMA_WRITE_BURST 0x2
69 #define EMA_READ_BURST 0x2
74 * ####################################
76 * ####################################
80 * Hardware Init/Uninit Functions
82 static inline void init_pmu(void);
83 static inline void uninit_pmu(void);
84 static inline void reset_ppe(struct platform_device
*pdev
);
85 static inline void init_ema(void);
86 static inline void init_mailbox(void);
87 static inline void init_atm_tc(void);
88 static inline void clear_share_buffer(void);
93 * ####################################
95 * ####################################
99 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
100 #define IFX_PMU_MODULE_PPE_TC BIT(21)
101 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
102 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
103 #define IFX_PMU_MODULE_TPE BIT(13)
104 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
107 * ####################################
109 * ####################################
112 static inline void init_pmu(void)
114 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01
|
115 IFX_PMU_MODULE_PPE_TC
|
116 IFX_PMU_MODULE_PPE_EMA
|
118 IFX_PMU_MODULE_DSL_DFE
);
121 static inline void uninit_pmu(void)
123 ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01
|
124 IFX_PMU_MODULE_PPE_TC
|
125 IFX_PMU_MODULE_PPE_EMA
|
127 IFX_PMU_MODULE_DSL_DFE
);
130 static inline void reset_ppe(struct platform_device
*pdev
)
133 /*unsigned int etop_cfg;
134 unsigned int etop_mdio_cfg;
135 unsigned int etop_ig_plen_ctrl;
136 unsigned int enet_mac_cfg;
138 etop_cfg = *IFX_PP32_ETOP_CFG;
139 etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
140 etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
141 enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
143 *IFX_PP32_ETOP_CFG &= ~0x03C0;
146 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
148 *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
149 *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
150 *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
151 *IFX_PP32_ETOP_CFG = etop_cfg;*/
155 static inline void init_ema(void)
157 // Configure share buffer master selection
161 IFX_REG_W32((EMA_CMD_BUF_LEN
<< 16) | (EMA_CMD_BASE_ADDR
>> 2), EMA_CMDCFG
);
162 IFX_REG_W32((EMA_DATA_BUF_LEN
<< 16) | (EMA_DATA_BASE_ADDR
>> 2), EMA_DATACFG
);
163 IFX_REG_W32(0x000000FF, EMA_IER
);
164 IFX_REG_W32(EMA_READ_BURST
| (EMA_WRITE_BURST
<< 2), EMA_CFG
);
167 static inline void init_mailbox(void)
169 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC
);
170 IFX_REG_W32(0x00000000, MBOX_IGU1_IER
);
171 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC
);
172 IFX_REG_W32(0x00000000, MBOX_IGU3_IER
);
175 static inline void init_atm_tc(void)
177 IFX_REG_W32(0x0F00, DREG_AT_CTRL
);
178 IFX_REG_W32(0x3C00, DREG_AR_CTRL
);
179 IFX_REG_W32(0x0, DREG_AT_IDLE0
);
180 IFX_REG_W32(0x0, DREG_AT_IDLE1
);
181 IFX_REG_W32(0x0, DREG_AR_IDLE0
);
182 IFX_REG_W32(0x0, DREG_AR_IDLE1
);
183 IFX_REG_W32(0x0, RFBI_CFG
);
184 IFX_REG_W32(0x1600, SFSM_DBA0
);
185 IFX_REG_W32(0x1721, SFSM_DBA1
);
186 IFX_REG_W32(0x1842, SFSM_CBA0
);
187 IFX_REG_W32(0x1853, SFSM_CBA1
);
188 IFX_REG_W32(0x14011, SFSM_CFG0
);
189 IFX_REG_W32(0x14011, SFSM_CFG1
);
190 IFX_REG_W32(0x1864, FFSM_DBA0
);
191 IFX_REG_W32(0x1930, FFSM_DBA1
);
192 IFX_REG_W32(0x3000C, FFSM_CFG0
);
193 IFX_REG_W32(0x3000C, FFSM_CFG1
);
194 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0
);
195 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1
);
198 static inline void clear_share_buffer(void)
200 volatile u32
*p
= SB_RAM0_ADDR(0);
203 for ( i
= 0; i
< SB_RAM0_DWLEN
+ SB_RAM1_DWLEN
+ SB_RAM2_DWLEN
+ SB_RAM3_DWLEN
; i
++ )
209 * Download PPE firmware binary code.
211 * src --- u32 *, binary code buffer
212 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
217 static inline int pp32_download_code(u32
*code_src
, unsigned int code_dword_len
, u32
*data_src
, unsigned int data_dword_len
)
221 if ( code_src
== 0 || ((unsigned long)code_src
& 0x03) != 0
222 || data_src
== 0 || ((unsigned long)data_src
& 0x03) != 0 )
225 if ( code_dword_len
<= CDM_CODE_MEMORYn_DWLEN(0) )
226 IFX_REG_W32(0x00, CDM_CFG
);
228 IFX_REG_W32(0x04, CDM_CFG
);
231 dest
= CDM_CODE_MEMORY(0, 0);
232 while ( code_dword_len
-- > 0 )
233 IFX_REG_W32(*code_src
++, dest
++);
236 dest
= CDM_DATA_MEMORY(0, 0);
237 while ( data_dword_len
-- > 0 )
238 IFX_REG_W32(*data_src
++, dest
++);
246 * ####################################
248 * ####################################
251 extern void ifx_ptm_get_fw_ver(unsigned int *major
, unsigned int *minor
)
253 ASSERT(major
!= NULL
, "pointer is NULL");
254 ASSERT(minor
!= NULL
, "pointer is NULL");
256 *major
= FW_VER_ID
->major
;
257 *minor
= FW_VER_ID
->minor
;
260 void ifx_ptm_init_chip(struct platform_device
*pdev
)
272 clear_share_buffer();
275 void ifx_ptm_uninit_chip(void)
282 * Initialize and start up PP32.
289 int ifx_pp32_start(int pp32
)
293 /* download firmware */
294 ret
= pp32_download_code(firmware_binary_code
, sizeof(firmware_binary_code
) / sizeof(*firmware_binary_code
), firmware_binary_data
, sizeof(firmware_binary_data
) / sizeof(*firmware_binary_data
));
299 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL
);
301 /* idle for a while to let PP32 init itself */
315 void ifx_pp32_stop(int pp32
)
318 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL
);