package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_danube.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_ptm_danube.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : PTM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : PTM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/reset.h>
  45 #include <linux/delay.h>
  46
  47 /*
  48  *  Chip Specific Head File
  49  */
  50 #include "ifxmips_ptm_adsl.h"
  51 #include "ifxmips_ptm_fw_danube.h"
  52
  53 #include <lantiq_soc.h>
  54
  55 /*
  56  * ####################################
  57  *              Definition
  58  * ####################################
  59  */
  60
  61 /*
  62  *  EMA Settings
  63  */
  64 #define EMA_CMD_BUF_LEN      0x0040
  65 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
  66 #define EMA_DATA_BUF_LEN     0x0100
  67 #define EMA_DATA_BASE_ADDR   (0x00000B00 << 2)
  68 #define EMA_WRITE_BURST      0x2
  69 #define EMA_READ_BURST       0x2
  70
  71
  72
  73 /*
  74  * ####################################
  75  *             Declaration
  76  * ####################################
  77  */
  78
  79 /*
  80  *  Hardware Init/Uninit Functions
  81  */
  82 static inline void init_pmu(void);
  83 static inline void uninit_pmu(void);
  84 static inline void reset_ppe(struct platform_device *pdev);
  85 static inline void init_ema(void);
  86 static inline void init_mailbox(void);
  87 static inline void init_atm_tc(void);
  88 static inline void clear_share_buffer(void);
  89
  90
  91
  92 /*
  93  * ####################################
  94  *            Local Variable
  95  * ####################################
  96  */
  97
  98
  99 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
 100 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
 101 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
 102 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
 103 #define IFX_PMU_MODULE_TPE       BIT(13)
 104 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
 105
 106 /*
 107  * ####################################
 108  *            Local Function
 109  * ####################################
 110  */
 111
 112 static inline void init_pmu(void)
 113 {
 114         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
 115                 IFX_PMU_MODULE_PPE_TC |
 116                 IFX_PMU_MODULE_PPE_EMA |
 117                 IFX_PMU_MODULE_TPE |
 118                 IFX_PMU_MODULE_DSL_DFE);
 119 }
 120
 121 static inline void uninit_pmu(void)
 122 {
 123         ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |
 124                 IFX_PMU_MODULE_PPE_TC |
 125                 IFX_PMU_MODULE_PPE_EMA |
 126                 IFX_PMU_MODULE_TPE |
 127                 IFX_PMU_MODULE_DSL_DFE);
 128 }
 129
 130 static inline void reset_ppe(struct platform_device *pdev)
 131 {
 132 #ifdef MODULE
 133     /*unsigned int etop_cfg;
 134     unsigned int etop_mdio_cfg;
 135     unsigned int etop_ig_plen_ctrl;
 136     unsigned int enet_mac_cfg;
 137
 138     etop_cfg            = *IFX_PP32_ETOP_CFG;
 139     etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;
 140     etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;
 141     enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;
 142
 143     *IFX_PP32_ETOP_CFG &= ~0x03C0;
 144
 145     //  reset PPE
 146     ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
 147
 148     *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;
 149     *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
 150     *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;
 151     *IFX_PP32_ETOP_CFG          = etop_cfg;*/
 152 #endif
 153 }
 154
 155 static inline void init_ema(void)
 156 {
 157     //  Configure share buffer master selection
 158         *SB_MST_SEL |= 0x03;
 159
 160     //  EMA Settings
 161     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 162     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 163     IFX_REG_W32(0x000000FF, EMA_IER);
 164     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 165 }
 166
 167 static inline void init_mailbox(void)
 168 {
 169     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 170     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 171     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 172     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 173 }
 174
 175 static inline void init_atm_tc(void)
 176 {
 177     IFX_REG_W32(0x0F00,     DREG_AT_CTRL);
 178     IFX_REG_W32(0x3C00,     DREG_AR_CTRL);
 179     IFX_REG_W32(0x0,        DREG_AT_IDLE0);
 180     IFX_REG_W32(0x0,        DREG_AT_IDLE1);
 181     IFX_REG_W32(0x0,        DREG_AR_IDLE0);
 182     IFX_REG_W32(0x0,        DREG_AR_IDLE1);
 183     IFX_REG_W32(0x0,        RFBI_CFG);
 184     IFX_REG_W32(0x1600,     SFSM_DBA0);
 185     IFX_REG_W32(0x1721,     SFSM_DBA1);
 186     IFX_REG_W32(0x1842,     SFSM_CBA0);
 187     IFX_REG_W32(0x1853,     SFSM_CBA1);
 188     IFX_REG_W32(0x14011,    SFSM_CFG0);
 189     IFX_REG_W32(0x14011,    SFSM_CFG1);
 190     IFX_REG_W32(0x1864,     FFSM_DBA0);
 191     IFX_REG_W32(0x1930,     FFSM_DBA1);
 192     IFX_REG_W32(0x3000C,    FFSM_CFG0);
 193     IFX_REG_W32(0x3000C,    FFSM_CFG1);
 194     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
 195     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
 196 }
 197
 198 static inline void clear_share_buffer(void)
 199 {
 200     volatile u32 *p = SB_RAM0_ADDR(0);
 201     unsigned int i;
 202
 203     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 204         IFX_REG_W32(0, p++);
 205 }
 206
 207 /*
 208  *  Description:
 209  *    Download PPE firmware binary code.
 210  *  Input:
 211  *    src       --- u32 *, binary code buffer
 212  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 213  *  Output:
 214  *    int       --- 0:    Success
 215  *                  else:           Error Code
 216  */
 217 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 218 {
 219     volatile u32 *dest;
 220
 221     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 222         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 223         return -1;
 224
 225     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 226         IFX_REG_W32(0x00, CDM_CFG);
 227     else
 228         IFX_REG_W32(0x04, CDM_CFG);
 229
 230     /*  copy code   */
 231     dest = CDM_CODE_MEMORY(0, 0);
 232     while ( code_dword_len-- > 0 )
 233         IFX_REG_W32(*code_src++, dest++);
 234
 235     /*  copy data   */
 236     dest = CDM_DATA_MEMORY(0, 0);
 237     while ( data_dword_len-- > 0 )
 238         IFX_REG_W32(*data_src++, dest++);
 239
 240     return 0;
 241 }
 242
 243
 244
 245 /*
 246  * ####################################
 247  *           Global Function
 248  * ####################################
 249  */
 250
 251 extern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
 252 {
 253     ASSERT(major != NULL, "pointer is NULL");
 254     ASSERT(minor != NULL, "pointer is NULL");
 255
 256     *major = FW_VER_ID->major;
 257     *minor = FW_VER_ID->minor;
 258 }
 259
 260 void ifx_ptm_init_chip(struct platform_device *pdev)
 261 {
 262     init_pmu();
 263
 264     reset_ppe(pdev);
 265
 266     init_ema();
 267
 268     init_mailbox();
 269
 270     init_atm_tc();
 271
 272     clear_share_buffer();
 273 }
 274
 275 void ifx_ptm_uninit_chip(void)
 276 {
 277     uninit_pmu();
 278 }
 279
 280 /*
 281  *  Description:
 282  *    Initialize and start up PP32.
 283  *  Input:
 284  *    none
 285  *  Output:
 286  *    int  --- 0: Success
 287  *             else:        Error Code
 288  */
 289 int ifx_pp32_start(int pp32)
 290 {
 291     int ret;
 292
 293     /*  download firmware   */
 294     ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 295     if ( ret != 0 )
 296         return ret;
 297
 298     /*  run PP32    */
 299     IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
 300
 301     /*  idle for a while to let PP32 init itself    */
 302     udelay(10);
 303
 304     return 0;
 305 }
 306
 307 /*
 308  *  Description:
 309  *    Halt PP32.
 310  *  Input:
 311  *    none
 312  *  Output:
 313  *    none
 314  */
 315 void ifx_pp32_stop(int pp32)
 316 {
 317     /*  halt PP32   */
 318     IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
 319 }