1 /******************************************************************************
3 ** FILE NAME : ifxmips_ptm_vdsl.c
9 ** DESCRIPTION : PTM driver common source file (core functions for VR9)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
24 #include <linux/version.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/ctype.h>
29 #include <linux/errno.h>
30 #include <linux/proc_fs.h>
31 #include <linux/init.h>
32 #include <linux/ioctl.h>
33 #include <linux/etherdevice.h>
34 #include <linux/interrupt.h>
36 #include "ifxmips_ptm_vdsl.h"
37 #include <lantiq_soc.h>
39 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
40 #define MODULE_PARM(a, b) module_param(a, int, 0)
42 static int wanqos_en
= 0;
43 static int queue_gamma_map
[4] = {0xFE, 0x01, 0x00, 0x00};
45 MODULE_PARM(wanqos_en
, "i");
46 MODULE_PARM_DESC(wanqos_en
, "WAN QoS support, 1 - enabled, 0 - disabled.");
48 MODULE_PARM_ARRAY(queue_gamma_map
, "4-4i");
49 MODULE_PARM_DESC(queue_gamma_map
, "TX QoS queues mapping to 4 TX Gamma interfaces.");
51 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
52 extern int (*ifx_mei_atm_showtime_exit
)(void);
53 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
55 static int g_showtime
= 0;
56 static void *g_xdata_addr
= NULL
;
59 #define ENABLE_TMP_DBG 0
61 unsigned long cgu_get_pp32_clock(void)
63 struct clk
*c
= clk_get_ppe();
64 unsigned long rate
= clk_get_rate(c
);
69 static void ptm_setup(struct net_device
*, int);
70 static struct net_device_stats
*ptm_get_stats(struct net_device
*);
71 static int ptm_open(struct net_device
*);
72 static int ptm_stop(struct net_device
*);
73 static unsigned int ptm_poll(int, unsigned int);
74 static int ptm_napi_poll(struct napi_struct
*, int);
75 static int ptm_hard_start_xmit(struct sk_buff
*, struct net_device
*);
76 static int ptm_ioctl(struct net_device
*, struct ifreq
*, int);
77 static void ptm_tx_timeout(struct net_device
*);
79 static inline struct sk_buff
* alloc_skb_rx(void);
80 static inline struct sk_buff
* alloc_skb_tx(unsigned int);
81 static inline struct sk_buff
*get_skb_pointer(unsigned int);
82 static inline int get_tx_desc(unsigned int, unsigned int *);
85 * Mailbox handler and signal function
87 static irqreturn_t
mailbox_irq_handler(int, void *);
90 * Tasklet to Handle Swap Descriptors
92 static void do_swap_desc_tasklet(unsigned long);
96 * Init & clean-up functions
98 static inline int init_priv_data(void);
99 static inline void clear_priv_data(void);
100 static inline int init_tables(void);
101 static inline void clear_tables(void);
103 static int g_wanqos_en
= 0;
105 static int g_queue_gamma_map
[4];
107 static struct ptm_priv_data g_ptm_priv_data
;
109 static struct net_device_ops g_ptm_netdev_ops
= {
110 .ndo_get_stats
= ptm_get_stats
,
111 .ndo_open
= ptm_open
,
112 .ndo_stop
= ptm_stop
,
113 .ndo_start_xmit
= ptm_hard_start_xmit
,
114 .ndo_validate_addr
= eth_validate_addr
,
115 .ndo_set_mac_address
= eth_mac_addr
,
116 .ndo_change_mtu
= eth_change_mtu
,
117 .ndo_do_ioctl
= ptm_ioctl
,
118 .ndo_tx_timeout
= ptm_tx_timeout
,
121 static struct net_device
*g_net_dev
[1] = {0};
122 static char *g_net_dev_name
[1] = {"ptm0"};
124 static int g_ptm_prio_queue_map
[8];
126 static DECLARE_TASKLET(g_swap_desc_tasklet
, do_swap_desc_tasklet
, 0);
129 unsigned int ifx_ptm_dbg_enable
= DBG_ENABLE_MASK_ERR
;
132 * ####################################
134 * ####################################
137 static void ptm_setup(struct net_device
*dev
, int ndev
)
139 dev
->netdev_ops
= &g_ptm_netdev_ops
;
140 netif_napi_add(dev
, &g_ptm_priv_data
.itf
[ndev
].napi
, ptm_napi_poll
, 16);
141 dev
->watchdog_timeo
= ETH_WATCHDOG_TIMEOUT
;
143 dev
->dev_addr
[0] = 0x00;
144 dev
->dev_addr
[1] = 0x20;
145 dev
->dev_addr
[2] = 0xda;
146 dev
->dev_addr
[3] = 0x86;
147 dev
->dev_addr
[4] = 0x23;
148 dev
->dev_addr
[5] = 0x75 + ndev
;
151 static struct net_device_stats
*ptm_get_stats(struct net_device
*dev
)
153 struct net_device_stats
*s
;
155 if ( dev
!= g_net_dev
[0] )
157 s
= &g_ptm_priv_data
.itf
[0].stats
;
162 static int ptm_open(struct net_device
*dev
)
164 ASSERT(dev
== g_net_dev
[0], "incorrect device");
166 napi_enable(&g_ptm_priv_data
.itf
[0].napi
);
168 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER
);
170 netif_start_queue(dev
);
175 static int ptm_stop(struct net_device
*dev
)
177 ASSERT(dev
== g_net_dev
[0], "incorrect device");
179 IFX_REG_W32_MASK(1 | (1 << 17), 0, MBOX_IGU1_IER
);
181 napi_disable(&g_ptm_priv_data
.itf
[0].napi
);
183 netif_stop_queue(dev
);
188 static unsigned int ptm_poll(int ndev
, unsigned int work_to_do
)
190 unsigned int work_done
= 0;
191 volatile struct rx_descriptor
*desc
;
192 struct rx_descriptor reg_desc
;
193 struct sk_buff
*skb
, *new_skb
;
195 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
197 while ( work_done
< work_to_do
) {
198 desc
= &WAN_RX_DESC_BASE
[g_ptm_priv_data
.itf
[0].rx_desc_pos
];
199 if ( desc
->own
/* || !desc->c */ ) // if PP32 hold descriptor or descriptor not completed
201 if ( ++g_ptm_priv_data
.itf
[0].rx_desc_pos
== WAN_RX_DESC_NUM
)
202 g_ptm_priv_data
.itf
[0].rx_desc_pos
= 0;
205 skb
= get_skb_pointer(reg_desc
.dataptr
);
206 ASSERT(skb
!= NULL
, "invalid pointer skb == NULL");
208 new_skb
= alloc_skb_rx();
209 if ( new_skb
!= NULL
) {
210 skb_reserve(skb
, reg_desc
.byteoff
);
211 skb_put(skb
, reg_desc
.datalen
);
213 // parse protocol header
214 skb
->dev
= g_net_dev
[0];
215 skb
->protocol
= eth_type_trans(skb
, skb
->dev
);
217 g_net_dev
[0]->last_rx
= jiffies
;
219 netif_receive_skb(skb
);
221 g_ptm_priv_data
.itf
[0].stats
.rx_packets
++;
222 g_ptm_priv_data
.itf
[0].stats
.rx_bytes
+= reg_desc
.datalen
;
224 reg_desc
.dataptr
= (unsigned int)new_skb
->data
& 0x0FFFFFFF;
225 reg_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
228 reg_desc
.datalen
= RX_MAX_BUFFER_SIZE
- RX_HEAD_MAC_ADDR_ALIGNMENT
;
232 /* write discriptor to memory */
233 *((volatile unsigned int *)desc
+ 1) = *((unsigned int *)®_desc
+ 1);
235 *(volatile unsigned int *)desc
= *(unsigned int *)®_desc
;
243 static int ptm_napi_poll(struct napi_struct
*napi
, int budget
)
246 unsigned int work_done
;
248 work_done
= ptm_poll(ndev
, budget
);
251 if ( !netif_running(napi
->dev
) ) {
257 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_ISRC
);
259 if (work_done
< budget
) {
261 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER
);
269 static int ptm_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
273 volatile struct tx_descriptor
*desc
;
274 struct tx_descriptor reg_desc
= {0};
275 struct sk_buff
*skb_to_free
;
276 unsigned int byteoff
;
278 ASSERT(dev
== g_net_dev
[0], "incorrect device");
281 err("not in showtime");
282 goto PTM_HARD_START_XMIT_FAIL
;
285 /* allocate descriptor */
286 desc_base
= get_tx_desc(0, &f_full
);
288 dev
->trans_start
= jiffies
;
289 netif_stop_queue(dev
);
291 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_ISRC
);
292 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_IER
);
295 goto PTM_HARD_START_XMIT_FAIL
;
296 desc
= &CPU_TO_WAN_TX_DESC_BASE
[desc_base
];
298 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
299 if ( skb_headroom(skb
) < sizeof(struct sk_buff
*) + byteoff
|| skb_cloned(skb
) ) {
300 struct sk_buff
*new_skb
;
302 ASSERT(skb_headroom(skb
) >= sizeof(struct sk_buff
*) + byteoff
, "skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff");
303 ASSERT(!skb_cloned(skb
), "skb is cloned");
305 new_skb
= alloc_skb_tx(skb
->len
);
306 if ( new_skb
== NULL
) {
308 goto ALLOC_SKB_TX_FAIL
;
310 skb_put(new_skb
, skb
->len
);
311 memcpy(new_skb
->data
, skb
->data
, skb
->len
);
312 dev_kfree_skb_any(skb
);
314 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
315 /* write back to physical memory */
316 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
319 *(struct sk_buff
**)((unsigned int)skb
->data
- byteoff
- sizeof(struct sk_buff
*)) = skb
;
320 /* write back to physical memory */
321 dma_cache_wback((unsigned long)skb
->data
- byteoff
- sizeof(struct sk_buff
*), skb
->len
+ byteoff
+ sizeof(struct sk_buff
*));
323 /* free previous skb */
324 skb_to_free
= get_skb_pointer(desc
->dataptr
);
325 if ( skb_to_free
!= NULL
)
326 dev_kfree_skb_any(skb_to_free
);
328 /* update descriptor */
330 reg_desc
.dataptr
= (unsigned int)skb
->data
& (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT
- 1));
331 reg_desc
.datalen
= skb
->len
< ETH_ZLEN
? ETH_ZLEN
: skb
->len
;
332 reg_desc
.qid
= g_ptm_prio_queue_map
[skb
->priority
> 7 ? 7 : skb
->priority
];
333 reg_desc
.byteoff
= byteoff
;
336 reg_desc
.sop
= reg_desc
.eop
= 1;
339 g_ptm_priv_data
.itf
[0].stats
.tx_packets
++;
340 g_ptm_priv_data
.itf
[0].stats
.tx_bytes
+= reg_desc
.datalen
;
342 /* write discriptor to memory */
343 *((volatile unsigned int *)desc
+ 1) = *((unsigned int *)®_desc
+ 1);
345 *(volatile unsigned int *)desc
= *(unsigned int *)®_desc
;
347 dev
->trans_start
= jiffies
;
352 PTM_HARD_START_XMIT_FAIL
:
353 dev_kfree_skb_any(skb
);
354 g_ptm_priv_data
.itf
[0].stats
.tx_dropped
++;
358 static int ptm_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
360 ASSERT(dev
== g_net_dev
[0], "incorrect device");
364 case IFX_PTM_MIB_CW_GET
:
365 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxNoIdleCodewords
= IFX_REG_R32(DREG_AR_CELL0
) + IFX_REG_R32(DREG_AR_CELL1
);
366 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxIdleCodewords
= IFX_REG_R32(DREG_AR_IDLE_CNT0
) + IFX_REG_R32(DREG_AR_IDLE_CNT1
);
367 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxCodingViolation
= IFX_REG_R32(DREG_AR_CVN_CNT0
) + IFX_REG_R32(DREG_AR_CVN_CNT1
) + IFX_REG_R32(DREG_AR_CVNP_CNT0
) + IFX_REG_R32(DREG_AR_CVNP_CNT1
);
368 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxNoIdleCodewords
= IFX_REG_R32(DREG_AT_CELL0
) + IFX_REG_R32(DREG_AT_CELL1
);
369 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxIdleCodewords
= IFX_REG_R32(DREG_AT_IDLE_CNT0
) + IFX_REG_R32(DREG_AT_IDLE_CNT1
);
371 case IFX_PTM_MIB_FRAME_GET
:
373 PTM_FRAME_MIB_T data
= {0};
376 data
.RxCorrect
= IFX_REG_R32(DREG_AR_HEC_CNT0
) + IFX_REG_R32(DREG_AR_HEC_CNT1
) + IFX_REG_R32(DREG_AR_AIIDLE_CNT0
) + IFX_REG_R32(DREG_AR_AIIDLE_CNT1
);
377 for ( i
= 0; i
< 4; i
++ )
378 data
.RxDropped
+= WAN_RX_MIB_TABLE(i
)->wrx_dropdes_pdu
;
379 for ( i
= 0; i
< 8; i
++ )
380 data
.TxSend
+= WAN_TX_MIB_TABLE(i
)->wtx_total_pdu
;
382 *((PTM_FRAME_MIB_T
*)ifr
->ifr_data
) = data
;
385 case IFX_PTM_CFG_GET
:
386 // use bear channel 0 preemption gamma interface settings
387 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcPresent
= 1;
388 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
= RX_GAMMA_ITF_CFG(0)->rx_eth_fcs_ver_dis
== 0 ? 1 : 0;
389 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
= RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis
== 0 ? 1 : 0;;
390 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
= RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
== 0 ? 0 : (RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
* 16);
391 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
= TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis
== 0 ? 1 : 0;
392 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
= TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
== 0 ? 0 : 1;
393 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
= TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
== 0 ? 0 : (TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
* 16);
395 case IFX_PTM_CFG_SET
:
399 for ( i
= 0; i
< 4; i
++ ) {
400 RX_GAMMA_ITF_CFG(i
)->rx_eth_fcs_ver_dis
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
? 0 : 1;
402 RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
? 0 : 1;
404 switch ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
) {
405 case 16: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
= 1; break;
406 case 32: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
= 2; break;
407 default: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
= 0;
410 TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
? 0 : 1;
412 if ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
) {
413 switch ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
) {
414 case 16: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 1; break;
415 case 32: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 2; break;
416 default: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 0;
420 TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 0;
424 case IFX_PTM_MAP_PKT_PRIO_TO_Q
:
426 struct ppe_prio_q_map cmd
;
428 if ( copy_from_user(&cmd
, ifr
->ifr_data
, sizeof(cmd
)) )
431 if ( cmd
.pkt_prio
< 0 || cmd
.pkt_prio
>= ARRAY_SIZE(g_ptm_prio_queue_map
) )
434 if ( cmd
.qid
< 0 || cmd
.qid
>= g_wanqos_en
)
437 g_ptm_prio_queue_map
[cmd
.pkt_prio
] = cmd
.qid
;
447 static void ptm_tx_timeout(struct net_device
*dev
)
449 ASSERT(dev
== g_net_dev
[0], "incorrect device");
451 /* disable TX irq, release skb when sending new packet */
452 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER
);
454 /* wake up TX queue */
455 netif_wake_queue(dev
);
460 static inline struct sk_buff
* alloc_skb_rx(void)
464 /* allocate memroy including trailer and padding */
465 skb
= dev_alloc_skb(RX_MAX_BUFFER_SIZE
+ DATA_BUFFER_ALIGNMENT
);
467 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
468 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
469 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
470 /* pub skb in reserved area "skb->data - 4" */
471 *((struct sk_buff
**)skb
->data
- 1) = skb
;
473 /* write back and invalidate cache */
474 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
475 /* invalidate cache */
476 dma_cache_inv((unsigned long)skb
->data
, (unsigned int)skb
->end
- (unsigned int)skb
->data
);
482 static inline struct sk_buff
* alloc_skb_tx(unsigned int size
)
486 /* allocate memory including padding */
487 size
= RX_MAX_BUFFER_SIZE
;
488 size
= (size
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1);
489 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
490 /* must be burst length alignment */
492 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
496 static inline struct sk_buff
*get_skb_pointer(unsigned int dataptr
)
498 unsigned int skb_dataptr
;
501 // usually, CPE memory is less than 256M bytes
502 // so NULL means invalid pointer
503 if ( dataptr
== 0 ) {
504 dbg("dataptr is 0, it's supposed to be invalid pointer");
508 skb_dataptr
= (dataptr
- 4) | KSEG1
;
509 skb
= *(struct sk_buff
**)skb_dataptr
;
511 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
512 ASSERT((((unsigned int)skb
->data
& (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT
- 1))) | KSEG1
) == (dataptr
| KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
517 static inline int get_tx_desc(unsigned int itf
, unsigned int *f_full
)
520 struct ptm_itf
*p_itf
= &g_ptm_priv_data
.itf
[0];
522 // assume TX is serial operation
523 // no protection provided
527 if ( CPU_TO_WAN_TX_DESC_BASE
[p_itf
->tx_desc_pos
].own
== 0 ) {
528 desc_base
= p_itf
->tx_desc_pos
;
529 if ( ++(p_itf
->tx_desc_pos
) == CPU_TO_WAN_TX_DESC_NUM
)
530 p_itf
->tx_desc_pos
= 0;
531 if ( CPU_TO_WAN_TX_DESC_BASE
[p_itf
->tx_desc_pos
].own
== 0 )
538 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
543 isr
= IFX_REG_R32(MBOX_IGU1_ISR
);
544 IFX_REG_W32(isr
, MBOX_IGU1_ISRC
);
545 isr
&= IFX_REG_R32(MBOX_IGU1_IER
);
548 IFX_REG_W32_MASK(1, 0, MBOX_IGU1_IER
);
549 napi_schedule(&g_ptm_priv_data
.itf
[0].napi
);
550 #if defined(ENABLE_TMP_DBG) && ENABLE_TMP_DBG
552 volatile struct rx_descriptor
*desc
= &WAN_RX_DESC_BASE
[g_ptm_priv_data
.itf
[0].rx_desc_pos
];
554 if ( desc
->own
) { // PP32 hold
555 err("invalid interrupt");
561 IFX_REG_W32_MASK(1 << 16, 0, MBOX_IGU1_IER
);
562 tasklet_hi_schedule(&g_swap_desc_tasklet
);
565 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER
);
566 netif_wake_queue(g_net_dev
[0]);
572 static void do_swap_desc_tasklet(unsigned long arg
)
575 volatile struct tx_descriptor
*desc
;
577 unsigned int byteoff
;
579 while ( budget
-- > 0 ) {
580 if ( WAN_SWAP_DESC_BASE
[g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
].own
) // if PP32 hold descriptor
583 desc
= &WAN_SWAP_DESC_BASE
[g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
];
584 if ( ++g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
== WAN_SWAP_DESC_NUM
)
585 g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
= 0;
587 skb
= get_skb_pointer(desc
->dataptr
);
589 dev_kfree_skb_any(skb
);
591 skb
= alloc_skb_tx(RX_MAX_BUFFER_SIZE
);
593 panic("can't allocate swap buffer for PPE firmware use\n");
594 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
595 *(struct sk_buff
**)((unsigned int)skb
->data
- byteoff
- sizeof(struct sk_buff
*)) = skb
;
597 desc
->dataptr
= (unsigned int)skb
->data
& 0x0FFFFFFF;
602 IFX_REG_W32_MASK(0, 16, MBOX_IGU1_ISRC
);
603 // no more skb to be replaced
604 if ( WAN_SWAP_DESC_BASE
[g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
].own
) { // if PP32 hold descriptor
605 IFX_REG_W32_MASK(0, 1 << 16, MBOX_IGU1_IER
);
609 tasklet_hi_schedule(&g_swap_desc_tasklet
);
614 static inline int ifx_ptm_version(char *buf
)
617 unsigned int major
, minor
;
619 ifx_ptm_get_fw_ver(&major
, &minor
);
621 len
+= sprintf(buf
+ len
, "PTM %d.%d.%d", IFX_PTM_VER_MAJOR
, IFX_PTM_VER_MID
, IFX_PTM_VER_MINOR
);
622 len
+= sprintf(buf
+ len
, " PTM (E1) firmware version %d.%d\n", major
, minor
);
627 static inline int init_priv_data(void)
631 g_wanqos_en
= wanqos_en
? wanqos_en
: 8;
632 if ( g_wanqos_en
> 8 )
635 for ( i
= 0; i
< ARRAY_SIZE(g_queue_gamma_map
); i
++ )
637 g_queue_gamma_map
[i
] = queue_gamma_map
[i
] & ((1 << g_wanqos_en
) - 1);
638 for ( j
= 0; j
< i
; j
++ )
639 g_queue_gamma_map
[i
] &= ~g_queue_gamma_map
[j
];
642 memset(&g_ptm_priv_data
, 0, sizeof(g_ptm_priv_data
));
645 int max_packet_priority
= ARRAY_SIZE(g_ptm_prio_queue_map
);
647 int q_step
, q_accum
, p_step
;
649 tx_num_q
= __ETH_WAN_TX_QUEUE_NUM
;
650 q_step
= tx_num_q
- 1;
651 p_step
= max_packet_priority
- 1;
652 for ( j
= 0, q_accum
= 0; j
< max_packet_priority
; j
++, q_accum
+= q_step
)
653 g_ptm_prio_queue_map
[j
] = q_step
- (q_accum
+ (p_step
>> 1)) / p_step
;
659 static inline void clear_priv_data(void)
663 static inline int init_tables(void)
665 struct sk_buff
*skb_pool
[WAN_RX_DESC_NUM
] = {0};
666 struct cfg_std_data_len cfg_std_data_len
= {0};
667 struct tx_qos_cfg tx_qos_cfg
= {0};
668 struct psave_cfg psave_cfg
= {0};
669 struct eg_bwctrl_cfg eg_bwctrl_cfg
= {0};
670 struct test_mode test_mode
= {0};
671 struct rx_bc_cfg rx_bc_cfg
= {0};
672 struct tx_bc_cfg tx_bc_cfg
= {0};
673 struct gpio_mode gpio_mode
= {0};
674 struct gpio_wm_cfg gpio_wm_cfg
= {0};
675 struct rx_gamma_itf_cfg rx_gamma_itf_cfg
= {0};
676 struct tx_gamma_itf_cfg tx_gamma_itf_cfg
= {0};
677 struct wtx_qos_q_desc_cfg wtx_qos_q_desc_cfg
= {0};
678 struct rx_descriptor rx_desc
= {0};
679 struct tx_descriptor tx_desc
= {0};
682 for ( i
= 0; i
< WAN_RX_DESC_NUM
; i
++ ) {
683 skb_pool
[i
] = alloc_skb_rx();
684 if ( skb_pool
[i
] == NULL
)
685 goto ALLOC_SKB_RX_FAIL
;
688 cfg_std_data_len
.byte_off
= RX_HEAD_MAC_ADDR_ALIGNMENT
; // this field replaces byte_off in rx descriptor of VDSL ingress
689 cfg_std_data_len
.data_len
= 1600;
690 *CFG_STD_DATA_LEN
= cfg_std_data_len
;
692 tx_qos_cfg
.time_tick
= cgu_get_pp32_clock() / 62500; // 16 * (cgu_get_pp32_clock() / 1000000)
693 tx_qos_cfg
.overhd_bytes
= 0;
694 tx_qos_cfg
.eth1_eg_qnum
= __ETH_WAN_TX_QUEUE_NUM
;
695 tx_qos_cfg
.eth1_burst_chk
= 1;
696 tx_qos_cfg
.eth1_qss
= 0;
697 tx_qos_cfg
.shape_en
= 0; // disable
698 tx_qos_cfg
.wfq_en
= 0; // strict priority
699 *TX_QOS_CFG
= tx_qos_cfg
;
701 psave_cfg
.start_state
= 0;
702 psave_cfg
.sleep_en
= 1; // enable sleep mode
703 *PSAVE_CFG
= psave_cfg
;
705 eg_bwctrl_cfg
.fdesc_wm
= 16;
706 eg_bwctrl_cfg
.class_len
= 128;
707 *EG_BWCTRL_CFG
= eg_bwctrl_cfg
;
709 //*GPIO_ADDR = (unsigned int)IFX_GPIO_P0_OUT;
710 *GPIO_ADDR
= (unsigned int)0x00000000; // disabled by default
712 gpio_mode
.gpio_bit_bc1
= 2;
713 gpio_mode
.gpio_bit_bc0
= 1;
714 gpio_mode
.gpio_bc1_en
= 0;
715 gpio_mode
.gpio_bc0_en
= 0;
716 *GPIO_MODE
= gpio_mode
;
718 gpio_wm_cfg
.stop_wm_bc1
= 2;
719 gpio_wm_cfg
.start_wm_bc1
= 4;
720 gpio_wm_cfg
.stop_wm_bc0
= 2;
721 gpio_wm_cfg
.start_wm_bc0
= 4;
722 *GPIO_WM_CFG
= gpio_wm_cfg
;
724 test_mode
.mib_clear_mode
= 0;
725 test_mode
.test_mode
= 0;
726 *TEST_MODE
= test_mode
;
728 rx_bc_cfg
.local_state
= 0;
729 rx_bc_cfg
.remote_state
= 0;
730 rx_bc_cfg
.to_false_th
= 7;
731 rx_bc_cfg
.to_looking_th
= 3;
732 *RX_BC_CFG(0) = rx_bc_cfg
;
733 *RX_BC_CFG(1) = rx_bc_cfg
;
735 tx_bc_cfg
.fill_wm
= 2;
736 tx_bc_cfg
.uflw_wm
= 2;
737 *TX_BC_CFG(0) = tx_bc_cfg
;
738 *TX_BC_CFG(1) = tx_bc_cfg
;
740 rx_gamma_itf_cfg
.receive_state
= 0;
741 rx_gamma_itf_cfg
.rx_min_len
= 60;
742 rx_gamma_itf_cfg
.rx_pad_en
= 1;
743 rx_gamma_itf_cfg
.rx_eth_fcs_ver_dis
= 0;
744 rx_gamma_itf_cfg
.rx_rm_eth_fcs
= 1;
745 rx_gamma_itf_cfg
.rx_tc_crc_ver_dis
= 0;
746 rx_gamma_itf_cfg
.rx_tc_crc_size
= 1;
747 rx_gamma_itf_cfg
.rx_eth_fcs_result
= 0xC704DD7B;
748 rx_gamma_itf_cfg
.rx_tc_crc_result
= 0x1D0F1D0F;
749 rx_gamma_itf_cfg
.rx_crc_cfg
= 0x2500;
750 rx_gamma_itf_cfg
.rx_eth_fcs_init_value
= 0xFFFFFFFF;
751 rx_gamma_itf_cfg
.rx_tc_crc_init_value
= 0x0000FFFF;
752 rx_gamma_itf_cfg
.rx_max_len_sel
= 0;
753 rx_gamma_itf_cfg
.rx_edit_num2
= 0;
754 rx_gamma_itf_cfg
.rx_edit_pos2
= 0;
755 rx_gamma_itf_cfg
.rx_edit_type2
= 0;
756 rx_gamma_itf_cfg
.rx_edit_en2
= 0;
757 rx_gamma_itf_cfg
.rx_edit_num1
= 0;
758 rx_gamma_itf_cfg
.rx_edit_pos1
= 0;
759 rx_gamma_itf_cfg
.rx_edit_type1
= 0;
760 rx_gamma_itf_cfg
.rx_edit_en1
= 0;
761 rx_gamma_itf_cfg
.rx_inserted_bytes_1l
= 0;
762 rx_gamma_itf_cfg
.rx_inserted_bytes_1h
= 0;
763 rx_gamma_itf_cfg
.rx_inserted_bytes_2l
= 0;
764 rx_gamma_itf_cfg
.rx_inserted_bytes_2h
= 0;
765 rx_gamma_itf_cfg
.rx_len_adj
= -6;
766 for ( i
= 0; i
< 4; i
++ )
767 *RX_GAMMA_ITF_CFG(i
) = rx_gamma_itf_cfg
;
769 tx_gamma_itf_cfg
.tx_len_adj
= 6;
770 tx_gamma_itf_cfg
.tx_crc_off_adj
= 6;
771 tx_gamma_itf_cfg
.tx_min_len
= 0;
772 tx_gamma_itf_cfg
.tx_eth_fcs_gen_dis
= 0;
773 tx_gamma_itf_cfg
.tx_tc_crc_size
= 1;
774 tx_gamma_itf_cfg
.tx_crc_cfg
= 0x2F00;
775 tx_gamma_itf_cfg
.tx_eth_fcs_init_value
= 0xFFFFFFFF;
776 tx_gamma_itf_cfg
.tx_tc_crc_init_value
= 0x0000FFFF;
777 for ( i
= 0; i
< ARRAY_SIZE(g_queue_gamma_map
); i
++ ) {
778 tx_gamma_itf_cfg
.queue_mapping
= g_queue_gamma_map
[i
];
779 *TX_GAMMA_ITF_CFG(i
) = tx_gamma_itf_cfg
;
782 for ( i
= 0; i
< __ETH_WAN_TX_QUEUE_NUM
; i
++ ) {
783 wtx_qos_q_desc_cfg
.length
= WAN_TX_DESC_NUM
;
784 wtx_qos_q_desc_cfg
.addr
= __ETH_WAN_TX_DESC_BASE(i
);
785 *WTX_QOS_Q_DESC_CFG(i
) = wtx_qos_q_desc_cfg
;
788 // default TX queue QoS config is all ZERO
791 IFX_REG_W32(0x90111293, TX_CTRL_K_TABLE(0));
792 IFX_REG_W32(0x14959617, TX_CTRL_K_TABLE(1));
793 IFX_REG_W32(0x18999A1B, TX_CTRL_K_TABLE(2));
794 IFX_REG_W32(0x9C1D1E9F, TX_CTRL_K_TABLE(3));
795 IFX_REG_W32(0xA02122A3, TX_CTRL_K_TABLE(4));
796 IFX_REG_W32(0x24A5A627, TX_CTRL_K_TABLE(5));
797 IFX_REG_W32(0x28A9AA2B, TX_CTRL_K_TABLE(6));
798 IFX_REG_W32(0xAC2D2EAF, TX_CTRL_K_TABLE(7));
799 IFX_REG_W32(0x30B1B233, TX_CTRL_K_TABLE(8));
800 IFX_REG_W32(0xB43536B7, TX_CTRL_K_TABLE(9));
801 IFX_REG_W32(0xB8393ABB, TX_CTRL_K_TABLE(10));
802 IFX_REG_W32(0x3CBDBE3F, TX_CTRL_K_TABLE(11));
803 IFX_REG_W32(0xC04142C3, TX_CTRL_K_TABLE(12));
804 IFX_REG_W32(0x44C5C647, TX_CTRL_K_TABLE(13));
805 IFX_REG_W32(0x48C9CA4B, TX_CTRL_K_TABLE(14));
806 IFX_REG_W32(0xCC4D4ECF, TX_CTRL_K_TABLE(15));
808 // init RX descriptor
813 rx_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
814 rx_desc
.datalen
= RX_MAX_BUFFER_SIZE
- RX_HEAD_MAC_ADDR_ALIGNMENT
;
815 for ( i
= 0; i
< WAN_RX_DESC_NUM
; i
++ ) {
816 rx_desc
.dataptr
= (unsigned int)skb_pool
[i
]->data
& 0x0FFFFFFF;
817 WAN_RX_DESC_BASE
[i
] = rx_desc
;
820 // init TX descriptor
830 for ( i
= 0; i
< CPU_TO_WAN_TX_DESC_NUM
; i
++ )
831 CPU_TO_WAN_TX_DESC_BASE
[i
] = tx_desc
;
832 for ( i
= 0; i
< WAN_TX_DESC_NUM_TOTAL
; i
++ )
833 WAN_TX_DESC_BASE(0)[i
] = tx_desc
;
835 // init Swap descriptor
836 for ( i
= 0; i
< WAN_SWAP_DESC_NUM
; i
++ )
837 WAN_SWAP_DESC_BASE
[i
] = tx_desc
;
839 // init fastpath TX descriptor
841 for ( i
= 0; i
< FASTPATH_TO_WAN_TX_DESC_NUM
; i
++ )
842 FASTPATH_TO_WAN_TX_DESC_BASE
[i
] = tx_desc
;
848 dev_kfree_skb_any(skb_pool
[i
]);
852 static inline void clear_tables(void)
857 for ( i
= 0; i
< WAN_RX_DESC_NUM
; i
++ ) {
858 skb
= get_skb_pointer(WAN_RX_DESC_BASE
[i
].dataptr
);
860 dev_kfree_skb_any(skb
);
863 for ( i
= 0; i
< CPU_TO_WAN_TX_DESC_NUM
; i
++ ) {
864 skb
= get_skb_pointer(CPU_TO_WAN_TX_DESC_BASE
[i
].dataptr
);
866 dev_kfree_skb_any(skb
);
869 for ( j
= 0; j
< 8; j
++ )
870 for ( i
= 0; i
< WAN_TX_DESC_NUM
; i
++ ) {
871 skb
= get_skb_pointer(WAN_TX_DESC_BASE(j
)[i
].dataptr
);
873 dev_kfree_skb_any(skb
);
876 for ( i
= 0; i
< WAN_SWAP_DESC_NUM
; i
++ ) {
877 skb
= get_skb_pointer(WAN_SWAP_DESC_BASE
[i
].dataptr
);
879 dev_kfree_skb_any(skb
);
882 for ( i
= 0; i
< FASTPATH_TO_WAN_TX_DESC_NUM
; i
++ ) {
883 skb
= get_skb_pointer(FASTPATH_TO_WAN_TX_DESC_BASE
[i
].dataptr
);
885 dev_kfree_skb_any(skb
);
889 static int ptm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
891 ASSERT(port_cell
!= NULL
, "port_cell is NULL");
892 ASSERT(xdata_addr
!= NULL
, "xdata_addr is NULL");
894 // TODO: ReTX set xdata_addr
895 g_xdata_addr
= xdata_addr
;
899 IFX_REG_W32(0x0F, UTP_CFG
);
902 // IFX_REG_W32_MASK(1 << 17, 0, FFSM_CFG0);
905 printk("enter showtime\n");
910 static int ptm_showtime_exit(void)
916 // IFX_REG_W32_MASK(0, 1 << 17, FFSM_CFG0);
919 IFX_REG_W32(0x00, UTP_CFG
);
923 // TODO: ReTX clean state
926 printk("leave showtime\n");
933 static int ifx_ptm_init(void)
938 struct port_cell_info port_cell
= {0};
940 ret
= init_priv_data();
942 err("INIT_PRIV_DATA_FAIL");
943 goto INIT_PRIV_DATA_FAIL
;
949 err("INIT_TABLES_FAIL");
950 goto INIT_TABLES_FAIL
;
953 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
954 g_net_dev
[i
] = alloc_netdev(0, g_net_dev_name
[i
], NET_NAME_UNKNOWN
, ether_setup
);
955 if ( g_net_dev
[i
] == NULL
)
956 goto ALLOC_NETDEV_FAIL
;
957 ptm_setup(g_net_dev
[i
], i
);
960 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
961 ret
= register_netdev(g_net_dev
[i
]);
963 goto REGISTER_NETDEV_FAIL
;
966 /* register interrupt handler */
967 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, IRQF_DISABLED
, "ptm_mailbox_isr", &g_ptm_priv_data
);
969 if ( ret
== -EBUSY
) {
970 err("IRQ may be occupied by other driver, please reconfig to disable it.");
973 err("request_irq fail");
975 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
977 disable_irq(PPE_MAILBOX_IGU1_INT
);
979 ret
= ifx_pp32_start(0);
981 err("ifx_pp32_start fail!");
982 goto PP32_START_FAIL
;
984 IFX_REG_W32(1 << 16, MBOX_IGU1_IER
); // enable SWAP interrupt
985 IFX_REG_W32(~0, MBOX_IGU1_ISRC
);
987 enable_irq(PPE_MAILBOX_IGU1_INT
);
989 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &g_xdata_addr
);
991 ifx_mei_atm_showtime_enter
= ptm_showtime_enter
;
992 ifx_mei_atm_showtime_exit
= ptm_showtime_exit
;
994 ifx_ptm_version(ver_str
);
995 printk(KERN_INFO
"%s", ver_str
);
997 printk("ifxmips_ptm: PTM init succeed\n");
1002 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1003 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1004 i
= ARRAY_SIZE(g_net_dev
);
1005 REGISTER_NETDEV_FAIL
:
1007 unregister_netdev(g_net_dev
[i
]);
1008 i
= ARRAY_SIZE(g_net_dev
);
1011 free_netdev(g_net_dev
[i
]);
1012 g_net_dev
[i
] = NULL
;
1015 INIT_PRIV_DATA_FAIL
:
1017 printk("ifxmips_ptm: PTM init failed\n");
1021 static void __exit
ifx_ptm_exit(void)
1024 ifx_mei_atm_showtime_enter
= NULL
;
1025 ifx_mei_atm_showtime_exit
= NULL
;
1030 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1032 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1033 unregister_netdev(g_net_dev
[i
]);
1035 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1036 free_netdev(g_net_dev
[i
]);
1037 g_net_dev
[i
] = NULL
;
1042 ifx_ptm_uninit_chip();
1048 static int __init
wanqos_en_setup(char *line
)
1050 wanqos_en
= simple_strtoul(line
, NULL
, 0);
1052 if ( wanqos_en
< 1 || wanqos_en
> 8 )
1058 static int __init
queue_gamma_map_setup(char *line
)
1063 for ( i
= 0, p
= line
; i
< ARRAY_SIZE(queue_gamma_map
) && isxdigit(*p
); i
++ )
1065 queue_gamma_map
[i
] = simple_strtoul(p
, &p
, 0);
1066 if ( *p
== ',' || *p
== ';' || *p
== ':' )
1073 module_init(ifx_ptm_init
);
1074 module_exit(ifx_ptm_exit
);
1076 __setup("wanqos_en=", wanqos_en_setup
);
1077 __setup("queue_gamma_map=", queue_gamma_map_setup
);
1080 MODULE_LICENSE("GPL");