lantiq: Update to the latest DSL driver / application versions
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-vdsl-mei / patches / 100-compat.patch
1 --- a/src/drv_mei_cpe_common.c
2 +++ b/src/drv_mei_cpe_common.c
3 @@ -19,7 +19,6 @@
4 /* get at first the driver configuration */
5 #include "drv_mei_cpe_config.h"
6
7 -#include "ifx_types.h"
8 #include "drv_mei_cpe_os.h"
9 #include "drv_mei_cpe_dbg.h"
10
11 --- a/src/drv_mei_cpe_linux.h
12 +++ b/src/drv_mei_cpe_linux.h
13 @@ -51,12 +51,6 @@
14 #include <linux/poll.h>
15 #include <linux/types.h>
16
17 -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
18 - #include <asm/ifx/ifx_types.h>
19 -#else
20 - #include <ifx_types.h>
21 -#endif
22 -
23 #endif /* #if (MEI_DRV_IFXOS_ENABLE == 0)*/
24
25 /* ============================================================================
26 --- a/src/drv_mei_cpe_linux.c
27 +++ b/src/drv_mei_cpe_linux.c
28 @@ -98,6 +98,8 @@
29
30 #include "drv_mei_cpe_api_atm_ptm_intern.h"
31
32 +#include <lantiq_soc.h>
33 +
34 /* ===================================
35 extern function declarations
36 =================================== */
37 @@ -1783,7 +1785,9 @@ static int __init MEI_module_init (void)
38 return (result);
39 }
40
41 +#if 0
42 ppa_callback_set(LTQ_MEI_SHOWTIME_CHECK, (void *)ltq_mei_atm_showtime_check);
43 +#endif
44
45 return 0;
46 }
47 @@ -1963,7 +1967,9 @@ static void MEI_module_exit (void)
48 ("MEI_DRV: Chipset Basic Exit failed" MEI_DRV_CRLF));
49 }
50
51 +#if 0
52 ppa_callback_set(LTQ_MEI_SHOWTIME_CHECK, (void *)NULL);
53 +#endif
54
55 /* touch one time this variable to avoid that the linker will remove it */
56 debug_level = MEI_DRV_PRN_LEVEL_OFF;
57 @@ -2120,21 +2126,32 @@ static int MEI_InitModuleBasics(void)
58 }
59
60 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
61 +
62 +#define PMU_DFE BIT(9)
63 +
64 static int MEI_SysClkEnable(struct clk *clk)
65 {
66 +#if 0
67 if (IS_ERR(clk))
68 return -1;
69 clk_enable(clk);
70 +#else
71 + ltq_pmu_enable(PMU_DFE);
72 +#endif
73
74 return 0;
75 }
76
77 static int MEI_SysClkDisable(struct clk *clk)
78 {
79 +#if 0
80 if (IS_ERR(clk))
81 return -1;
82 clk_disable(clk);
83 clk_put(clk);
84 +#else
85 + ltq_pmu_disable(PMU_DFE);
86 +#endif
87
88 return 0;
89 }
90 @@ -2454,11 +2471,15 @@ IFX_int32_t MEI_IoctlInitDevice(
91 pMeiDev->eModePoll = e_MEI_DEV_ACCESS_MODE_IRQ;
92 pMeiDev->intMask = ME_ARC2ME_INTERRUPT_UNMASK_ALL;
93
94 +#if 1
95 + virq = (IFX_uint32_t)pInitDev->usedIRQ;
96 +#else
97 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
98 virq = (IFX_uint32_t)pInitDev->usedIRQ;
99 #else
100 virq = irq_create_mapping(NULL, (IFX_uint32_t)pInitDev->usedIRQ);
101 #endif
102 +#endif
103
104 pTmpXCntrl = MEI_VrxXDevToIrqListAdd(
105 MEI_DRV_LINENUM_GET(pMeiDev),
106 --- a/src/drv_mei_cpe_api_atm_ptm_intern.c
107 +++ b/src/drv_mei_cpe_api_atm_ptm_intern.c
108 @@ -193,6 +193,51 @@ int ifx_mei_atm_led_blink(void)
109 return IFX_SUCCESS;
110 }
111
112 +#if MEI_MAX_DFE_CHAN_DEVICES > 1
113 +#error "Compat functions do not support MEI_MAX_DFE_CHAN_DEVICES > 1 yet"
114 +#else
115 +int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
116 +int (*ifx_mei_atm_showtime_exit)(void) = NULL;
117 +
118 +ltq_ifx_mei_atm_showtime_enter_compat(IFX_uint8_t dslLineNum,
119 + struct port_cell_info *cellInfo,
120 + void *xdata) {
121 + if (ifx_mei_atm_showtime_enter)
122 + return ifx_mei_atm_showtime_enter(cellInfo, xdata);
123 +
124 + return -e_MEI_ERR_OP_FAILED;
125 +}
126 +
127 +ltq_ifx_mei_atm_showtime_exit_compat(IFX_uint8_t dslLineNum) {
128 + if (ifx_mei_atm_showtime_exit)
129 + return ifx_mei_atm_showtime_exit();
130 +
131 + return -e_MEI_ERR_OP_FAILED;
132 +}
133 +
134 +void* ppa_callback_get(e_ltq_mei_cb_type type) {
135 + switch (type) {
136 + case LTQ_MEI_SHOWTIME_ENTER:
137 + return &ltq_ifx_mei_atm_showtime_enter_compat;
138 + case LTQ_MEI_SHOWTIME_EXIT:
139 + return &ltq_ifx_mei_atm_showtime_exit_compat;
140 + break;
141 + }
142 +
143 + BUG();
144 +}
145 +
146 +int ifx_mei_atm_showtime_check(int *is_showtime,
147 + struct port_cell_info *port_cell,
148 + void **xdata_addr) {
149 + return ltq_mei_atm_showtime_check(0, is_showtime, port_cell, xdata_addr);
150 +}
151 +
152 +EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
153 +EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
154 +EXPORT_SYMBOL(ifx_mei_atm_showtime_check);
155 +#endif
156 +
157 EXPORT_SYMBOL (MEI_InternalXtmSwhowtimeEntrySignal);
158 EXPORT_SYMBOL (MEI_InternalXtmSwhowtimeExitSignal);
159 EXPORT_SYMBOL(ifx_mei_atm_led_blink);
160 --- a/src/drv_mei_cpe_api_atm_ptm_intern.h
161 +++ b/src/drv_mei_cpe_api_atm_ptm_intern.h
162 @@ -21,7 +21,6 @@
163
164 #include "drv_mei_cpe_config.h"
165 #include "drv_mei_cpe_interface.h"
166 -#include <net/ppa_stack_al.h>
167
168 #if (MEI_EXPORT_INTERNAL_API == 1) && (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1)
169
170 @@ -42,8 +41,20 @@ extern IFX_int32_t MEI_InternalXtmSwhowt
171 MEI_DYN_CNTRL_T *pMeiDynCntrl,
172 MEI_XTM_ShowtimeExit_t *pArgXtm);
173
174 +#if 1
175 +typedef enum {
176 + LTQ_MEI_SHOWTIME_ENTER,
177 + LTQ_MEI_SHOWTIME_EXIT
178 +} e_ltq_mei_cb_type;
179 +
180 +typedef void (*ltq_mei_atm_showtime_enter_t)(IFX_uint8_t, struct port_cell_info *, void *);
181 +typedef void (*ltq_mei_atm_showtime_exit_t)(IFX_uint8_t);
182 +
183 +void* ppa_callback_get(e_ltq_mei_cb_type type);
184 +#else
185 extern int ppa_callback_set(e_ltq_mei_cb_type type, void *func);
186 extern void* ppa_callback_get(e_ltq_mei_cb_type type);
187 +#endif
188
189 int ltq_mei_atm_showtime_check (
190 const unsigned char line_idx,
191 --- a/src/drv_mei_cpe_device_vrx.c
192 +++ b/src/drv_mei_cpe_device_vrx.c
193 @@ -27,13 +27,6 @@
194 #include "drv_mei_cpe_mei_interface.h"
195 #include "drv_mei_cpe_api.h"
196
197 -#if defined(LINUX)
198 -# if (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))
199 -# include "ifx_pcie.h"
200 -# else
201 -# include "lantiq_pcie.h"
202 -# endif
203 -#endif /* #if defined(LINUX)*/
204
205 IFX_int32_t MEI_GPIntProcess(MEI_MeiRegVal_t processInt, MEI_DEV_T *pMeiDev)
206 {
207 @@ -81,6 +74,7 @@ IFX_int32_t MEI_GetChipInfo(MEI_DEV_T *p
208 */
209 IFX_int32_t MEI_VR10_PcieEntitiesCheck(IFX_uint8_t nEntityNum)
210 {
211 +#if 0
212 IFX_uint32_t pcie_entitiesNum;
213
214 /* get information from pcie driver */
215 @@ -101,6 +95,9 @@ IFX_int32_t MEI_VR10_PcieEntitiesCheck(I
216 }
217
218 return IFX_SUCCESS;
219 +#else
220 + return IFX_ERROR;
221 +#endif
222 }
223
224 /**
225 @@ -115,6 +112,7 @@ IFX_int32_t MEI_VR10_PcieEntitiesCheck(I
226 */
227 IFX_int32_t MEI_VR10_PcieEntityInit(MEI_MEI_DRV_CNTRL_T *pMeiDrvCntrl)
228 {
229 +#if 0
230 IFX_uint8_t entityNum;
231 ifx_pcie_ep_dev_t MEI_pcie_ep_dev;
232
233 @@ -137,6 +135,9 @@ IFX_int32_t MEI_VR10_PcieEntityInit(MEI_
234 pMeiDrvCntrl->MEI_pcie_irq = MEI_pcie_ep_dev.irq;
235
236 return IFX_SUCCESS;
237 +#else
238 + return IFX_ERROR;
239 +#endif
240 }
241
242 /**
243 @@ -151,6 +152,7 @@ IFX_int32_t MEI_VR10_PcieEntityInit(MEI_
244 */
245 IFX_int32_t MEI_VR10_PcieEntityFree(IFX_uint8_t entityNum)
246 {
247 +#if 0
248 if (ifx_pcie_ep_dev_info_release(entityNum))
249 {
250 PRN_ERR_USR_NL( MEI_DRV, MEI_DRV_PRN_LEVEL_ERR,
251 @@ -160,6 +162,9 @@ IFX_int32_t MEI_VR10_PcieEntityFree(IFX_
252 }
253
254 return IFX_SUCCESS;
255 +#else
256 + return IFX_ERROR;
257 +#endif
258 }
259
260 /**
261 @@ -174,6 +179,7 @@ IFX_int32_t MEI_VR10_PcieEntityFree(IFX_
262 */
263 IFX_int32_t MEI_VR10_InternalInitDevice(MEI_DYN_CNTRL_T *pMeiDynCntrl)
264 {
265 +#if 0
266 IFX_int32_t retVal;
267 IOCTL_MEI_devInit_t InitDev;
268 MEI_DEV_T *pMeiDev = pMeiDynCntrl->pMeiDev;
269 @@ -198,5 +204,8 @@ IFX_int32_t MEI_VR10_InternalInitDevice(
270 *MEI_GPIO_U32REG(GPIO_P0_ALSEL1) &= ~((1 << 0) | (1 << 3) | (1 << 8));
271
272 return IFX_SUCCESS;
273 +#else
274 + return IFX_ERROR;
275 +#endif
276 }
277