1 From 945359dd08b6d03c48f08094d3bd270fbe917114 Mon Sep 17 00:00:00 2001
2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
3 Date: Fri, 22 Jul 2016 11:40:13 -0400
4 Subject: [PATCH] rtl8xxxu: Implement rtl8188eu_config_channel()
6 The 8188eu doesn't seem to have REG_FPGA0_ANALOG2, so implement it's
9 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
11 .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 117 +++++++++++++++++++++
12 1 file changed, 117 insertions(+)
14 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
15 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
16 @@ -283,6 +283,122 @@ static struct rtl8xxxu_rfregval rtl8188e
20 +void rtl8188eu_config_channel(struct ieee80211_hw *hw)
22 + struct rtl8xxxu_priv *priv = hw->priv;
26 + int sec_ch_above, channel;
29 + opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
30 + rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
31 + channel = hw->conf.chandef.chan->hw_value;
33 + switch (hw->conf.chandef.width) {
34 + case NL80211_CHAN_WIDTH_20_NOHT:
36 + case NL80211_CHAN_WIDTH_20:
37 + opmode |= BW_OPMODE_20MHZ;
38 + rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
40 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
41 + val32 &= ~FPGA_RF_MODE;
42 + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
44 + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
45 + val32 &= ~FPGA_RF_MODE;
46 + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
48 + case NL80211_CHAN_WIDTH_40:
49 + if (hw->conf.chandef.center_freq1 >
50 + hw->conf.chandef.chan->center_freq) {
58 + opmode &= ~BW_OPMODE_20MHZ;
59 + rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
60 + rsr &= ~RSR_RSC_BANDWIDTH_40M;
62 + rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
64 + rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
65 + rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
67 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
68 + val32 |= FPGA_RF_MODE;
69 + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
71 + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
72 + val32 |= FPGA_RF_MODE;
73 + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
76 + * Set Control channel to upper or lower. These settings
77 + * are required only for 40MHz
79 + val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
80 + val32 &= ~CCK0_SIDEBAND;
82 + val32 |= CCK0_SIDEBAND;
83 + rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
85 + val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
86 + val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
88 + val32 |= OFDM_LSTF_PRIME_CH_LOW;
90 + val32 |= OFDM_LSTF_PRIME_CH_HIGH;
91 + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
93 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
94 + val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
96 + val32 |= FPGA0_PS_UPPER_CHANNEL;
98 + val32 |= FPGA0_PS_LOWER_CHANNEL;
99 + rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
106 + for (i = RF_A; i < priv->rf_paths; i++) {
107 + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
108 + val32 &= ~MODE_AG_CHANNEL_MASK;
110 + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
119 + rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
120 + rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
122 + rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
123 + rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
126 + for (i = RF_A; i < priv->rf_paths; i++) {
127 + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
128 + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
129 + val32 &= ~MODE_AG_CHANNEL_20MHZ;
131 + val32 |= MODE_AG_CHANNEL_20MHZ;
132 + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
136 static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv)
138 struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu;
139 @@ -1009,6 +1125,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
140 .init_phy_bb = rtl8188eu_init_phy_bb,
141 .init_phy_rf = rtl8188eu_init_phy_rf,
142 .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate,
143 + .config_channel = rtl8188eu_config_channel,
144 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
145 .usb_quirks = rtl8188e_usb_quirks,
146 .writeN_block_size = 128,