package/kernel/mac80211/patches/ath11k/0022-wifi-ath11k-update-hal-srng-regs-for-IPQ5018.patch

   1 From 711b80acbdfb9667a9cf8374e13320a6e624ce73 Mon Sep 17 00:00:00 2001
   2 From: Sriram R <quic_srirrama@quicinc.com>
   3 Date: Fri, 2 Dec 2022 23:37:14 +0200
   4 Subject: [PATCH] wifi: ath11k: update hal srng regs for IPQ5018
   5
   6 IPQ5018 hal srng register address & offsets are not
   7 similar to IPQ8074/IPQ6018/QCN9074, hence define a
   8 new set of srng register group data for IPQ5018.
   9
  10 Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1
  11
  12 Signed-off-by: Sriram R <quic_srirrama@quicinc.com>
  13 Co-developed-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
  14 Signed-off-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
  15 Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
  16 Link: https://lore.kernel.org/r/20221122132152.17771-6-quic_kathirve@quicinc.com
  17 ---
  18  drivers/net/wireless/ath/ath11k/core.c |  1 +
  19  drivers/net/wireless/ath/ath11k/hw.c   | 79 ++++++++++++++++++++++++++
  20  drivers/net/wireless/ath/ath11k/hw.h   |  1 +
  21  3 files changed, 81 insertions(+)
  22
  23 --- a/drivers/net/wireless/ath/ath11k/core.c
  24 +++ b/drivers/net/wireless/ath/ath11k/core.c
  25 @@ -634,6 +634,7 @@ static const struct ath11k_hw_params ath
  26                         .max_fft_bins = 1024,
  27                 },
  28                 .internal_sleep_clock = false,
  29 +               .regs = &ipq5018_regs,
  30                 .host_ce_config = ath11k_host_ce_config_qcn9074,
  31                 .ce_count = CE_CNT_5018,
  32                 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
  33 --- a/drivers/net/wireless/ath/ath11k/hw.c
  34 +++ b/drivers/net/wireless/ath/ath11k/hw.c
  35 @@ -2645,6 +2645,85 @@ static const struct ath11k_hw_tcl2wbm_rb
  36         },
  37  };
  38
  39 +const struct ath11k_hw_regs ipq5018_regs = {
  40 +       /* SW2TCL(x) R0 ring configuration address */
  41 +       .hal_tcl1_ring_base_lsb = 0x00000694,
  42 +       .hal_tcl1_ring_base_msb = 0x00000698,
  43 +       .hal_tcl1_ring_id =     0x0000069c,
  44 +       .hal_tcl1_ring_misc = 0x000006a4,
  45 +       .hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
  46 +       .hal_tcl1_ring_tp_addr_msb = 0x000006b4,
  47 +       .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
  48 +       .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
  49 +       .hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
  50 +       .hal_tcl1_ring_msi1_base_msb = 0x000006e0,
  51 +       .hal_tcl1_ring_msi1_data = 0x000006e4,
  52 +       .hal_tcl2_ring_base_lsb = 0x000006ec,
  53 +       .hal_tcl_ring_base_lsb = 0x0000079c,
  54 +
  55 +       /* TCL STATUS ring address */
  56 +       .hal_tcl_status_ring_base_lsb = 0x000008a4,
  57 +
  58 +       /* REO2SW(x) R0 ring configuration address */
  59 +       .hal_reo1_ring_base_lsb = 0x000001ec,
  60 +       .hal_reo1_ring_base_msb = 0x000001f0,
  61 +       .hal_reo1_ring_id = 0x000001f4,
  62 +       .hal_reo1_ring_misc = 0x000001fc,
  63 +       .hal_reo1_ring_hp_addr_lsb = 0x00000200,
  64 +       .hal_reo1_ring_hp_addr_msb = 0x00000204,
  65 +       .hal_reo1_ring_producer_int_setup = 0x00000210,
  66 +       .hal_reo1_ring_msi1_base_lsb = 0x00000234,
  67 +       .hal_reo1_ring_msi1_base_msb = 0x00000238,
  68 +       .hal_reo1_ring_msi1_data = 0x0000023c,
  69 +       .hal_reo2_ring_base_lsb = 0x00000244,
  70 +       .hal_reo1_aging_thresh_ix_0 = 0x00000564,
  71 +       .hal_reo1_aging_thresh_ix_1 = 0x00000568,
  72 +       .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
  73 +       .hal_reo1_aging_thresh_ix_3 = 0x00000570,
  74 +
  75 +       /* REO2SW(x) R2 ring pointers (head/tail) address */
  76 +       .hal_reo1_ring_hp = 0x00003028,
  77 +       .hal_reo1_ring_tp = 0x0000302c,
  78 +       .hal_reo2_ring_hp = 0x00003030,
  79 +
  80 +       /* REO2TCL R0 ring configuration address */
  81 +       .hal_reo_tcl_ring_base_lsb = 0x000003fc,
  82 +       .hal_reo_tcl_ring_hp = 0x00003058,
  83 +
  84 +       /* SW2REO ring address */
  85 +       .hal_sw2reo_ring_base_lsb = 0x0000013c,
  86 +       .hal_sw2reo_ring_hp = 0x00003018,
  87 +
  88 +       /* REO CMD ring address */
  89 +       .hal_reo_cmd_ring_base_lsb = 0x000000e4,
  90 +       .hal_reo_cmd_ring_hp = 0x00003010,
  91 +
  92 +       /* REO status address */
  93 +       .hal_reo_status_ring_base_lsb = 0x00000504,
  94 +       .hal_reo_status_hp = 0x00003070,
  95 +
  96 +       /* WCSS relative address */
  97 +       .hal_seq_wcss_umac_ce0_src_reg = 0x08400000
  98 +               - HAL_IPQ5018_CE_WFSS_REG_BASE,
  99 +       .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000
 100 +               - HAL_IPQ5018_CE_WFSS_REG_BASE,
 101 +       .hal_seq_wcss_umac_ce1_src_reg = 0x08402000
 102 +               - HAL_IPQ5018_CE_WFSS_REG_BASE,
 103 +       .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000
 104 +               - HAL_IPQ5018_CE_WFSS_REG_BASE,
 105 +
 106 +       /* WBM Idle address */
 107 +       .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
 108 +       .hal_wbm_idle_link_ring_misc = 0x00000884,
 109 +
 110 +       /* SW2WBM release address */
 111 +       .hal_wbm_release_ring_base_lsb = 0x000001ec,
 112 +
 113 +       /* WBM2SW release address */
 114 +       .hal_wbm0_release_ring_base_lsb = 0x00000924,
 115 +       .hal_wbm1_release_ring_base_lsb = 0x0000097c,
 116 +};
 117 +
 118  const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
 119         .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
 120         .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074,
 121 --- a/drivers/net/wireless/ath/ath11k/hw.h
 122 +++ b/drivers/net/wireless/ath/ath11k/hw.h
 123 @@ -415,6 +415,7 @@ extern const struct ath11k_hw_regs qca63
 124  extern const struct ath11k_hw_regs qcn9074_regs;
 125  extern const struct ath11k_hw_regs wcn6855_regs;
 126  extern const struct ath11k_hw_regs wcn6750_regs;
 127 +extern const struct ath11k_hw_regs ipq5018_regs;
 128
 129  static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
 130  {