1 From patchwork Sat Sep 17 20:27:41 2022
2 Content-Type: text/plain; charset="utf-8"
4 Content-Transfer-Encoding: 8bit
5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 12979247
7 X-Patchwork-Delegate: kvalo@adurom.com
8 Return-Path: <linux-wireless-owner@kernel.org>
9 Date: Sat, 17 Sep 2022 21:27:41 +0100
10 From: Daniel Golle <daniel@makrotopia.org>
11 To: linux-wireless@vger.kernel.org, Stanislaw Gruszka <stf_xl@wp.pl>,
12 Helmut Schaa <helmut.schaa@googlemail.com>
13 Cc: Kalle Valo <kvalo@kernel.org>,
14 "David S. Miller" <davem@davemloft.net>,
15 Eric Dumazet <edumazet@google.com>,
16 Jakub Kicinski <kuba@kernel.org>,
17 Paolo Abeni <pabeni@redhat.com>,
18 Johannes Berg <johannes.berg@intel.com>
19 Subject: [PATCH v3 06/16] rt2x00: add r calibration for MT7620
21 <e0c34f233089bec4eb73826bc4f512166ee25934.1663445157.git.daniel@makrotopia.org>
22 References: <cover.1663445157.git.daniel@makrotopia.org>
24 Content-Disposition: inline
25 In-Reply-To: <cover.1663445157.git.daniel@makrotopia.org>
27 List-ID: <linux-wireless.vger.kernel.org>
28 X-Mailing-List: linux-wireless@vger.kernel.org
30 From: Tomislav Požega <pozega.tomislav@gmail.com>
32 Add r calibration code as found in mtk driver.
34 Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
35 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
36 Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
38 v2: use rt2800_wait_bbp_rf_ready()
40 drivers/net/wireless/ralink/rt2x00/rt2800.h | 2 +
41 .../net/wireless/ralink/rt2x00/rt2800lib.c | 133 ++++++++++++++++++
42 2 files changed, 135 insertions(+)
44 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
45 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
48 #define MAC_STATUS_CFG 0x1200
49 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
50 +#define MAC_STATUS_CFG_BBP_RF_BUSY_TX FIELD32(0x00000001)
51 +#define MAC_STATUS_CFG_BBP_RF_BUSY_RX FIELD32(0x00000002)
55 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
56 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
57 @@ -8475,6 +8475,138 @@ static void rt2800_rf_self_txdc_cal(stru
58 rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
61 +static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
63 + int calcode = ((d2 - d1) * 1000) / 43;
65 + if ((calcode % 10) >= 5)
67 + calcode = (calcode / 10);
72 +static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
75 + u8 saverfb0r1, saverfb0r34, saverfb0r35;
76 + u8 saverfb5r4, saverfb5r17, saverfb5r18;
77 + u8 saverfb5r19, saverfb5r20;
78 + u8 savebbpr22, savebbpr47, savebbpr49;
82 + char d1 = 0, d2 = 0;
84 + u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
87 + saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
88 + saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
89 + saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
90 + saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
91 + saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
92 + saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
93 + saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
94 + saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
96 + savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
97 + savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
98 + savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
100 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
101 + MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
102 + MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
103 + MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
105 + maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
107 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
109 + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
110 + rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
112 + maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
114 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
116 + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
117 + rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
119 + rfvalue = (MAC_RF_BYPASS0 | 0x3004);
120 + rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
121 + rfvalue = (MAC_RF_CONTROL0 | (~0x3002));
122 + rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
124 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
125 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
126 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
127 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
128 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
130 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
131 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
132 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
134 + rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
136 + rt2800_bbp_write(rt2x00dev, 47, 0x04);
137 + rt2800_bbp_write(rt2x00dev, 22, 0x80);
138 + usleep_range(100, 200);
139 + bytevalue = rt2800_bbp_read(rt2x00dev, 49);
140 + if (bytevalue > 128)
141 + d1 = bytevalue - 256;
143 + d1 = (char)bytevalue;
144 + rt2800_bbp_write(rt2x00dev, 22, 0x0);
145 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
147 + rt2800_bbp_write(rt2x00dev, 22, 0x80);
148 + usleep_range(100, 200);
149 + bytevalue = rt2800_bbp_read(rt2x00dev, 49);
150 + if (bytevalue > 128)
151 + d2 = bytevalue - 256;
153 + d2 = (char)bytevalue;
154 + rt2800_bbp_write(rt2x00dev, 22, 0x0);
156 + rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
158 + r_cal_code = 256 + rcalcode;
160 + r_cal_code = (u8)rcalcode;
162 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
164 + rt2800_bbp_write(rt2x00dev, 22, 0x0);
166 + bytevalue = rt2800_bbp_read(rt2x00dev, 21);
168 + rt2800_bbp_write(rt2x00dev, 21, bytevalue);
169 + bytevalue = rt2800_bbp_read(rt2x00dev, 21);
170 + bytevalue &= (~0x1);
171 + rt2800_bbp_write(rt2x00dev, 21, bytevalue);
173 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
174 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
175 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
176 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
177 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
178 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
179 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
180 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
182 + rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
183 + rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
184 + rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
186 + rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
187 + rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
189 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
190 + rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
193 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
194 bool set_bw, bool is_ht40)
196 @@ -9082,6 +9214,7 @@ static void rt2800_init_rfcsr_6352(struc
197 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
198 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
200 + rt2800_r_calibration(rt2x00dev);
201 rt2800_rf_self_txdc_cal(rt2x00dev);
202 rt2800_bw_filter_calibration(rt2x00dev, true);
203 rt2800_bw_filter_calibration(rt2x00dev, false);