1 From d0e61a0f7cca51ce340a5a73595189972122ff25 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 24 Apr 2019 09:49:24 +0200
4 Subject: [PATCH] rt2x00: add RT3883 support
6 Patch add support for RT3883 chip. Code was taken direclty
7 from openwrt project and merge into one patch.
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
11 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
13 drivers/net/wireless/ralink/rt2x00/rt2800.h | 19 +-
14 .../net/wireless/ralink/rt2x00/rt2800lib.c | 598 +++++++++++++++++-
15 .../net/wireless/ralink/rt2x00/rt2800soc.c | 9 +-
16 3 files changed, 607 insertions(+), 19 deletions(-)
18 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
19 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
22 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
23 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
24 - * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
25 + * RF3053 2.4G/5G 3T3R(RT3563/RT3573/RT3593)
26 + * RF3853 2.4G/5G 3T3R(RT3883/RT3662)
34 +#define RF3853 0x3853
38 @@ -1726,6 +1728,20 @@
39 #define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
44 +#define TX_TXBF_CFG_0 0x138c
45 +#define TX_TXBF_CFG_1 0x13a4
46 +#define TX_TXBF_CFG_2 0x13a8
47 +#define TX_TXBF_CFG_3 0x13ac
52 +#define TX_FBK_CFG_3S_0 0x13c4
53 +#define TX_FBK_CFG_3S_1 0x13c8
56 * RX_FILTER_CFG: RX configuration register.
58 #define RX_FILTER_CFG 0x1400
59 @@ -2296,6 +2312,7 @@ struct mac_iveiv_entry {
63 +#define RFCSR2_RESCAL_BP FIELD8(0x40)
64 #define RFCSR2_RESCAL_EN FIELD8(0x80)
65 #define RFCSR2_RX2_EN_MT7620 FIELD8(0x02)
66 #define RFCSR2_TX2_EN_MT7620 FIELD8(0x20)
67 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
68 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
69 @@ -381,7 +381,8 @@ static unsigned int rt2800_eeprom_word_i
70 wiphy_name(rt2x00dev->hw->wiphy), word))
73 - if (rt2x00_rt(rt2x00dev, RT3593))
74 + if (rt2x00_rt(rt2x00dev, RT3593) ||
75 + rt2x00_rt(rt2x00dev, RT3883))
76 map = rt2800_eeprom_map_ext;
78 map = rt2800_eeprom_map;
79 @@ -590,6 +591,7 @@ void rt2800_get_txwi_rxwi_size(struct rt
81 switch (rt2x00dev->chip.rt) {
84 *txwi_size = TXWI_DESC_SIZE_4WORDS;
85 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
87 @@ -2180,7 +2182,8 @@ void rt2800_config_ant(struct rt2x00_dev
88 rt2800_bbp_write(rt2x00dev, 3, r3);
89 rt2800_bbp_write(rt2x00dev, 1, r1);
91 - if (rt2x00_rt(rt2x00dev, RT3593)) {
92 + if (rt2x00_rt(rt2x00dev, RT3593) ||
93 + rt2x00_rt(rt2x00dev, RT3883)) {
94 if (ant->rx_chain_num == 1)
95 rt2800_bbp_write(rt2x00dev, 86, 0x00);
97 @@ -2202,7 +2205,8 @@ static void rt2800_config_lna_gain(struc
98 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
99 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
100 } else if (libconf->rf.channel <= 128) {
101 - if (rt2x00_rt(rt2x00dev, RT3593)) {
102 + if (rt2x00_rt(rt2x00dev, RT3593) ||
103 + rt2x00_rt(rt2x00dev, RT3883)) {
104 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
105 lna_gain = rt2x00_get_field16(eeprom,
107 @@ -2212,7 +2216,8 @@ static void rt2800_config_lna_gain(struc
108 EEPROM_RSSI_BG2_LNA_A1);
111 - if (rt2x00_rt(rt2x00dev, RT3593)) {
112 + if (rt2x00_rt(rt2x00dev, RT3593) ||
113 + rt2x00_rt(rt2x00dev, RT3883)) {
114 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
115 lna_gain = rt2x00_get_field16(eeprom,
117 @@ -2880,6 +2885,211 @@ static void rt2800_config_channel_rf3053
121 +static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
122 + struct ieee80211_conf *conf,
123 + struct rf_channel *rf,
124 + struct channel_info *info)
128 + u8 pwr1, pwr2, pwr3;
130 + const bool txbf_enabled = false; /* TODO */
132 + /* TODO: add band selection */
134 + if (rf->channel <= 14)
135 + rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
136 + else if (rf->channel < 132)
137 + rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
139 + rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
141 + rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
142 + rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
144 + if (rf->channel <= 14)
145 + rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
147 + rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
149 + if (rf->channel <= 14)
150 + rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
152 + rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
154 + rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
156 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
157 + rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
158 + rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
159 + rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
160 + rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
161 + rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
162 + rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
163 + rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
164 + rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
166 + switch (rt2x00dev->default_ant.tx_chain_num) {
168 + rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
171 + rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
174 + rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
178 + switch (rt2x00dev->default_ant.rx_chain_num) {
180 + rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
183 + rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
186 + rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
189 + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
191 + rt2800_freq_cal_mode1(rt2x00dev);
193 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
194 + if (!conf_is_ht40(conf))
198 + rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
200 + if (rf->channel <= 14)
201 + rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
203 + rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
205 + if (conf_is_ht40(conf))
206 + rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
208 + rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
210 + if (rf->channel <= 14)
211 + rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
213 + rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
215 + /* loopback RF_BS */
216 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
217 + if (rf->channel <= 14)
218 + rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
220 + rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
221 + rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
223 + if (rf->channel <= 14)
225 + else if (rf->channel < 100)
227 + else if (rf->channel < 132)
235 + rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
237 + if (rf->channel <= 14)
238 + rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
240 + rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
242 + if (rf->channel <= 14)
244 + else if (rf->channel < 100)
246 + else if (rf->channel < 132)
250 + rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
252 + if (rf->channel <= 14)
260 + rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
262 + rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
264 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
265 + if (rf->channel <= 14)
266 + rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
268 + rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
270 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
271 + if (rf->channel <= 14)
272 + rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
274 + rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
276 + if (rf->channel <= 14) {
277 + pwr1 = info->default_power1 & 0x1f;
278 + pwr2 = info->default_power2 & 0x1f;
279 + pwr3 = info->default_power3 & 0x1f;
281 + pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
282 + (info->default_power1 & 0x7);
283 + pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
284 + (info->default_power2 & 0x7);
285 + pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
286 + (info->default_power3 & 0x7);
289 + rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
290 + rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
291 + rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
293 + rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
294 + rf->channel, pwr1, pwr2, pwr3);
296 + bbp = (info->default_power1 >> 5) |
297 + ((info->default_power2 & 0xe0) >> 1);
298 + rt2800_bbp_write(rt2x00dev, 109, bbp);
300 + bbp = rt2800_bbp_read(rt2x00dev, 110);
302 + bbp |= (info->default_power3 & 0xe0) >> 1;
303 + rt2800_bbp_write(rt2x00dev, 110, bbp);
305 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
306 + if (rf->channel <= 14)
307 + rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
309 + rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
311 + /* Enable RF tuning */
312 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
313 + rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
314 + rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
318 + bbp = rt2800_bbp_read(rt2x00dev, 49);
319 + /* clear update flag */
320 + rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
321 + rt2800_bbp_write(rt2x00dev, 49, bbp);
323 + /* TODO: add calibration for TxBF */
326 #define POWER_BOUND 0x27
327 #define POWER_BOUND_5G 0x2b
329 @@ -3683,19 +3893,51 @@ static char rt2800_txpower_to_dev(struct
330 unsigned int channel,
333 - if (rt2x00_rt(rt2x00dev, RT3593))
334 + if (rt2x00_rt(rt2x00dev, RT3593) ||
335 + rt2x00_rt(rt2x00dev, RT3883))
336 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
339 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
341 - if (rt2x00_rt(rt2x00dev, RT3593))
342 + if (rt2x00_rt(rt2x00dev, RT3593) ||
343 + rt2x00_rt(rt2x00dev, RT3883))
344 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
347 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
350 +static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
351 + struct rf_channel *rf)
355 + bbp = (rf->channel > 14) ? 0x48 : 0x38;
356 + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
358 + rt2800_bbp_write(rt2x00dev, 69, 0x12);
360 + if (rf->channel <= 14) {
361 + rt2800_bbp_write(rt2x00dev, 70, 0x0a);
363 + /* Disable CCK packet detection */
364 + rt2800_bbp_write(rt2x00dev, 70, 0x00);
367 + rt2800_bbp_write(rt2x00dev, 73, 0x10);
369 + if (rf->channel > 14) {
370 + rt2800_bbp_write(rt2x00dev, 62, 0x1d);
371 + rt2800_bbp_write(rt2x00dev, 63, 0x1d);
372 + rt2800_bbp_write(rt2x00dev, 64, 0x1d);
374 + rt2800_bbp_write(rt2x00dev, 62, 0x2d);
375 + rt2800_bbp_write(rt2x00dev, 63, 0x2d);
376 + rt2800_bbp_write(rt2x00dev, 64, 0x2d);
380 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
381 struct ieee80211_conf *conf,
382 struct rf_channel *rf,
383 @@ -3714,6 +3956,12 @@ static void rt2800_config_channel(struct
384 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
385 info->default_power3);
387 + switch (rt2x00dev->chip.rt) {
389 + rt3883_bbp_adjust(rt2x00dev, rf);
393 switch (rt2x00dev->chip.rf) {
396 @@ -3734,6 +3982,9 @@ static void rt2800_config_channel(struct
398 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
401 + rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
406 @@ -3815,6 +4066,15 @@ static void rt2800_config_channel(struct
407 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
408 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
409 rt2800_bbp_write(rt2x00dev, 77, 0x98);
410 + } else if (rt2x00_rt(rt2x00dev, RT3883)) {
411 + rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
412 + rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
413 + rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
415 + if (rt2x00dev->default_ant.rx_chain_num > 1)
416 + rt2800_bbp_write(rt2x00dev, 86, 0x46);
418 + rt2800_bbp_write(rt2x00dev, 86, 0);
420 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
421 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
422 @@ -3828,6 +4088,7 @@ static void rt2800_config_channel(struct
423 !rt2x00_rt(rt2x00dev, RT6352)) {
424 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
425 rt2800_bbp_write(rt2x00dev, 82, 0x62);
426 + rt2800_bbp_write(rt2x00dev, 82, 0x62);
427 rt2800_bbp_write(rt2x00dev, 75, 0x46);
429 if (rt2x00_rt(rt2x00dev, RT3593))
430 @@ -3836,19 +4097,22 @@ static void rt2800_config_channel(struct
431 rt2800_bbp_write(rt2x00dev, 82, 0x84);
432 rt2800_bbp_write(rt2x00dev, 75, 0x50);
434 - if (rt2x00_rt(rt2x00dev, RT3593))
435 + if (rt2x00_rt(rt2x00dev, RT3593) ||
436 + rt2x00_rt(rt2x00dev, RT3883))
437 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
441 if (rt2x00_rt(rt2x00dev, RT3572))
442 rt2800_bbp_write(rt2x00dev, 82, 0x94);
443 - else if (rt2x00_rt(rt2x00dev, RT3593))
444 + else if (rt2x00_rt(rt2x00dev, RT3593) ||
445 + rt2x00_rt(rt2x00dev, RT3883))
446 rt2800_bbp_write(rt2x00dev, 82, 0x82);
447 else if (!rt2x00_rt(rt2x00dev, RT6352))
448 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
450 - if (rt2x00_rt(rt2x00dev, RT3593))
451 + if (rt2x00_rt(rt2x00dev, RT3593) ||
452 + rt2x00_rt(rt2x00dev, RT3883))
453 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
455 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
456 @@ -3984,6 +4248,23 @@ static void rt2800_config_channel(struct
457 usleep_range(1000, 1500);
460 + if (rt2x00_rt(rt2x00dev, RT3883)) {
461 + if (!conf_is_ht40(conf))
462 + rt2800_bbp_write(rt2x00dev, 105, 0x34);
464 + rt2800_bbp_write(rt2x00dev, 105, 0x04);
467 + if (rf->channel <= 14)
468 + reg = 0x2e + rt2x00dev->lna_gain;
470 + reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
472 + rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
474 + usleep_range(1000, 1500);
477 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
479 if (!conf_is_ht40(conf)) {
480 @@ -4243,6 +4524,9 @@ static u8 rt2800_compensate_txpower(stru
481 if (rt2x00_rt(rt2x00dev, RT3593))
482 return min_t(u8, txpower, 0xc);
484 + if (rt2x00_rt(rt2x00dev, RT3883))
485 + return min_t(u8, txpower, 0xf);
487 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
489 * Check if eirp txpower exceed txpower_limit.
490 @@ -5004,7 +5288,8 @@ static void rt2800_config_txpower(struct
491 struct ieee80211_channel *chan,
494 - if (rt2x00_rt(rt2x00dev, RT3593))
495 + if (rt2x00_rt(rt2x00dev, RT3593) ||
496 + rt2x00_rt(rt2x00dev, RT3883))
497 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
498 else if (rt2x00_rt(rt2x00dev, RT6352))
499 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
500 @@ -5051,6 +5336,7 @@ void rt2800_vco_calibration(struct rt2x0
508 @@ -5251,7 +5537,8 @@ static u8 rt2800_get_default_vgc(struct
510 vgc = 0x2e + rt2x00dev->lna_gain;
511 } else { /* 5GHZ band */
512 - if (rt2x00_rt(rt2x00dev, RT3593))
513 + if (rt2x00_rt(rt2x00dev, RT3593) ||
514 + rt2x00_rt(rt2x00dev, RT3883))
515 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
516 else if (rt2x00_rt(rt2x00dev, RT5592))
517 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
518 @@ -5271,7 +5558,8 @@ static inline void rt2800_set_vgc(struct
520 if (qual->vgc_level != vgc_level) {
521 if (rt2x00_rt(rt2x00dev, RT3572) ||
522 - rt2x00_rt(rt2x00dev, RT3593)) {
523 + rt2x00_rt(rt2x00dev, RT3593) ||
524 + rt2x00_rt(rt2x00dev, RT3883)) {
525 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
527 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
528 @@ -5318,6 +5606,11 @@ void rt2800_link_tuner(struct rt2x00_dev
533 + if (qual->rssi > -65)
538 if (qual->rssi > -65)
540 @@ -5470,6 +5763,12 @@ static int rt2800_init_registers(struct
541 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
544 + } else if (rt2x00_rt(rt2x00dev, RT3883)) {
545 + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
546 + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
547 + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
548 + rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
549 + rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
550 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
551 rt2x00_rt(rt2x00dev, RT5392) ||
552 rt2x00_rt(rt2x00dev, RT6352)) {
553 @@ -5683,6 +5982,11 @@ static int rt2800_init_registers(struct
554 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
555 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
557 + if (rt2x00_rt(rt2x00dev, RT3883)) {
558 + rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
559 + rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
562 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
563 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
564 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
565 @@ -6299,6 +6603,47 @@ static void rt2800_init_bbp_3593(struct
566 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
569 +static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
571 + rt2800_init_bbp_early(rt2x00dev);
573 + rt2800_bbp_write(rt2x00dev, 4, 0x50);
574 + rt2800_bbp_write(rt2x00dev, 47, 0x48);
576 + rt2800_bbp_write(rt2x00dev, 86, 0x46);
577 + rt2800_bbp_write(rt2x00dev, 88, 0x90);
579 + rt2800_bbp_write(rt2x00dev, 92, 0x02);
581 + rt2800_bbp_write(rt2x00dev, 103, 0xc0);
582 + rt2800_bbp_write(rt2x00dev, 104, 0x92);
583 + rt2800_bbp_write(rt2x00dev, 105, 0x34);
584 + rt2800_bbp_write(rt2x00dev, 106, 0x12);
585 + rt2800_bbp_write(rt2x00dev, 120, 0x50);
586 + rt2800_bbp_write(rt2x00dev, 137, 0x0f);
587 + rt2800_bbp_write(rt2x00dev, 163, 0x9d);
589 + /* Set ITxBF timeout to 0x9C40=1000msec */
590 + rt2800_bbp_write(rt2x00dev, 179, 0x02);
591 + rt2800_bbp_write(rt2x00dev, 180, 0x00);
592 + rt2800_bbp_write(rt2x00dev, 182, 0x40);
593 + rt2800_bbp_write(rt2x00dev, 180, 0x01);
594 + rt2800_bbp_write(rt2x00dev, 182, 0x9c);
596 + rt2800_bbp_write(rt2x00dev, 179, 0x00);
598 + /* Reprogram the inband interface to put right values in RXWI */
599 + rt2800_bbp_write(rt2x00dev, 142, 0x04);
600 + rt2800_bbp_write(rt2x00dev, 143, 0x3b);
601 + rt2800_bbp_write(rt2x00dev, 142, 0x06);
602 + rt2800_bbp_write(rt2x00dev, 143, 0xa0);
603 + rt2800_bbp_write(rt2x00dev, 142, 0x07);
604 + rt2800_bbp_write(rt2x00dev, 143, 0xa1);
605 + rt2800_bbp_write(rt2x00dev, 142, 0x08);
606 + rt2800_bbp_write(rt2x00dev, 143, 0xa2);
607 + rt2800_bbp_write(rt2x00dev, 148, 0xc8);
610 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
613 @@ -6743,6 +7088,9 @@ static void rt2800_init_bbp(struct rt2x0
615 rt2800_init_bbp_3593(rt2x00dev);
618 + rt2800_init_bbp_3883(rt2x00dev);
622 rt2800_init_bbp_53xx(rt2x00dev);
623 @@ -7614,6 +7962,144 @@ static void rt2800_init_rfcsr_5350(struc
624 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
627 +static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
631 + /* TODO: get the actual ECO value from the SoC */
632 + const unsigned int eco = 5;
634 + rt2800_rf_init_calibration(rt2x00dev, 2);
636 + rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
637 + rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
638 + rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
639 + rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
640 + rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
641 + rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
642 + rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
643 + rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
644 + rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
645 + rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
646 + rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
647 + rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
648 + rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
649 + rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
650 + rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
651 + rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
652 + rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
654 + /* RFCSR 17 will be initialized later based on the
655 + * frequency offset stored in the EEPROM
658 + rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
659 + rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
660 + rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
661 + rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
662 + rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
663 + rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
664 + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
665 + rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
666 + rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
667 + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
668 + rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
669 + rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
670 + rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
671 + rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
672 + rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
673 + rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
674 + rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
675 + rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
676 + rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
677 + rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
678 + rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
679 + rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
680 + rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
681 + rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
682 + rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
683 + rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
684 + rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
685 + rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
686 + rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
687 + rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
688 + rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
689 + rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
690 + rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
691 + rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
692 + rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
693 + rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
694 + rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
695 + rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
696 + rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
697 + rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
698 + rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
699 + rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
700 + rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
701 + rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
702 + rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
703 + rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
705 + /* TODO: rx filter calibration? */
707 + rt2800_bbp_write(rt2x00dev, 137, 0x0f);
709 + rt2800_bbp_write(rt2x00dev, 163, 0x9d);
711 + rt2800_bbp_write(rt2x00dev, 105, 0x05);
713 + rt2800_bbp_write(rt2x00dev, 179, 0x02);
714 + rt2800_bbp_write(rt2x00dev, 180, 0x00);
715 + rt2800_bbp_write(rt2x00dev, 182, 0x40);
716 + rt2800_bbp_write(rt2x00dev, 180, 0x01);
717 + rt2800_bbp_write(rt2x00dev, 182, 0x9c);
719 + rt2800_bbp_write(rt2x00dev, 179, 0x00);
721 + rt2800_bbp_write(rt2x00dev, 142, 0x04);
722 + rt2800_bbp_write(rt2x00dev, 143, 0x3b);
723 + rt2800_bbp_write(rt2x00dev, 142, 0x06);
724 + rt2800_bbp_write(rt2x00dev, 143, 0xa0);
725 + rt2800_bbp_write(rt2x00dev, 142, 0x07);
726 + rt2800_bbp_write(rt2x00dev, 143, 0xa1);
727 + rt2800_bbp_write(rt2x00dev, 142, 0x08);
728 + rt2800_bbp_write(rt2x00dev, 143, 0xa2);
729 + rt2800_bbp_write(rt2x00dev, 148, 0xc8);
732 + rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
733 + rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
736 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
737 + rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
738 + rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
739 + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
741 + rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
742 + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
744 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
745 + rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
746 + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
748 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
750 + rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
752 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
754 + rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
756 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
758 + rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
760 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
762 + rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
765 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
767 rt2800_rf_init_calibration(rt2x00dev, 2);
768 @@ -8456,6 +8942,9 @@ static void rt2800_init_rfcsr(struct rt2
770 rt2800_init_rfcsr_3390(rt2x00dev);
773 + rt2800_init_rfcsr_3883(rt2x00dev);
776 rt2800_init_rfcsr_3572(rt2x00dev);
778 @@ -8661,7 +9150,8 @@ static u8 rt2800_get_txmixer_gain_24g(st
782 - if (rt2x00_rt(rt2x00dev, RT3593))
783 + if (rt2x00_rt(rt2x00dev, RT3593) ||
784 + rt2x00_rt(rt2x00dev, RT3883))
787 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
788 @@ -8675,7 +9165,8 @@ static u8 rt2800_get_txmixer_gain_5g(str
792 - if (rt2x00_rt(rt2x00dev, RT3593))
793 + if (rt2x00_rt(rt2x00dev, RT3593) ||
794 + rt2x00_rt(rt2x00dev, RT3883))
797 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
798 @@ -8781,7 +9272,8 @@ static int rt2800_validate_eeprom(struct
799 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
800 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
801 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
802 - if (!rt2x00_rt(rt2x00dev, RT3593)) {
803 + if (!rt2x00_rt(rt2x00dev, RT3593) &&
804 + !rt2x00_rt(rt2x00dev, RT3883)) {
805 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
806 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
807 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
808 @@ -8801,7 +9293,8 @@ static int rt2800_validate_eeprom(struct
809 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
810 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
811 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
812 - if (!rt2x00_rt(rt2x00dev, RT3593)) {
813 + if (!rt2x00_rt(rt2x00dev, RT3593) &&
814 + !rt2x00_rt(rt2x00dev, RT3883)) {
815 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
816 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
817 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
818 @@ -8809,7 +9302,8 @@ static int rt2800_validate_eeprom(struct
820 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
822 - if (rt2x00_rt(rt2x00dev, RT3593)) {
823 + if (rt2x00_rt(rt2x00dev, RT3593) ||
824 + rt2x00_rt(rt2x00dev, RT3883)) {
825 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
826 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
827 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
828 @@ -8848,6 +9342,8 @@ static int rt2800_init_eeprom(struct rt2
829 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
830 else if (rt2x00_rt(rt2x00dev, RT3352))
832 + else if (rt2x00_rt(rt2x00dev, RT3883))
834 else if (rt2x00_rt(rt2x00dev, RT5350))
837 @@ -8868,6 +9364,7 @@ static int rt2800_init_eeprom(struct rt2
845 @@ -9154,6 +9651,66 @@ static const struct rf_channel rf_vals_3
849 +static const struct rf_channel rf_vals_3853[] = {
879 + {102, 0x5b, 8, 10},
884 + {114, 0x5c, 8, 10},
889 + {126, 0x5d, 8, 10},
897 + {151, 0x5f, 8, 11},
909 static const struct rf_channel rf_vals_5592_xtal20[] = {
910 /* Channel, N, K, mod, R */
912 @@ -9417,6 +9974,11 @@ static int rt2800_probe_hw_mode(struct r
913 spec->channels = rf_vals_3x;
917 + spec->num_channels = ARRAY_SIZE(rf_vals_3853);
918 + spec->channels = rf_vals_3853;
922 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
923 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
924 @@ -9536,6 +10098,7 @@ static int rt2800_probe_hw_mode(struct r
932 @@ -9578,6 +10141,7 @@ static int rt2800_probe_rt(struct rt2x00
940 --- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c
941 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c
942 @@ -51,9 +51,16 @@ static bool rt2800soc_hwcrypt_disabled(s
944 static void rt2800soc_disable_radio(struct rt2x00_dev *rt2x00dev)
948 rt2800_disable_radio(rt2x00dev);
949 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
950 - rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
953 + if (rt2x00_rt(rt2x00dev, RT3883))
954 + rt2x00_set_field32(®, TX_PIN_CFG_RFTR_EN, 1);
956 + rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, reg);
959 static int rt2800soc_set_device_state(struct rt2x00_dev *rt2x00dev,