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9a237d9f3ca1e0d6764f7716c79b4d0c03fc341e
[openwrt/staging/mkresin.git] / package / ltq-vmmc / patches / 100-ifxmips.patch
1 --- a/src/drv_vmmc_access.h
2 +++ b/src/drv_vmmc_access.h
3 @@ -24,6 +24,10 @@
4 #include "drv_mps_vmmc.h"
5 #endif
6
7 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
8 +# define IFX_MPS IFXMIPS_MPS_BASE_ADDR
9 +#endif
10 +
11 /* ============================= */
12 /* Global Defines */
13 /* ============================= */
14 --- a/src/drv_vmmc_bbd.c
15 +++ b/src/drv_vmmc_bbd.c
16 @@ -1072,7 +1072,11 @@
17 IFX_uint8_t padBytes = 0;
18 #endif
19 IFX_uint16_t cram_offset, cram_crc,
20 - pCmd [MAX_CMD_WORD] = {0};
21 + pCmd [MAX_CMD_WORD]
22 +#if defined (__GNUC__) || defined (__GNUG__)
23 + __attribute__ ((aligned(4)))
24 +#endif
25 + = {0};
26
27 /* read offset */
28 cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t));
29 --- a/src/drv_vmmc_danube.h
30 +++ b/src/drv_vmmc_danube.h
31 @@ -15,56 +15,18 @@
32 */
33
34 #if defined SYSTEM_DANUBE
35 -#include <asm/ifx/ifx_gpio.h>
36 +#include <xway/xway.h>
37 +
38 #else
39 #error no system selected
40 #endif
41
42 -#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC
43 +#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC
44 /**
45
46 */
47 #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
48 do { \
49 - ret = VMMC_statusOk; \
50 - /* Reserve P0.0 as TDM/FSC */ \
51 - if (!GPIOreserved) \
52 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
53 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
54 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
55 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
56 - \
57 - /* Reserve P1.9 as TDM/DO */ \
58 - if (!GPIOreserved) \
59 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
60 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
61 - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
62 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
63 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
64 - \
65 - /* Reserve P1.10 as TDM/DI */ \
66 - if (!GPIOreserved) \
67 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
68 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
69 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\
70 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
71 - \
72 - /* Reserve P1.11 as TDM/DCL */ \
73 - if (!GPIOreserved) \
74 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
75 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
76 - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
77 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
78 - \
79 - if (mode == 2) { \
80 - /* TDM/FSC+DCL Master */ \
81 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
82 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
83 - } else { \
84 - /* TDM/FSC+DCL Slave */ \
85 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
86 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
87 - } \
88 } while(0);
89
90 /**
91 @@ -72,11 +34,6 @@
92 */
93 #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
94 do { \
95 - ret = VMMC_statusOk; \
96 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
97 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
98 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
99 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
100 } while (0)
101
102 #endif /* _DRV_VMMC_AMAZON_S_H */
103 --- a/src/drv_vmmc_init.c
104 +++ b/src/drv_vmmc_init.c
105 @@ -52,6 +52,14 @@
106 #include "ifx_pmu.h"
107 #endif /* PMU_SUPPORTED */
108
109 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
110 +# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
111 +# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
112 +# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
113 +# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
114 +# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
115 +# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
116 +#endif
117
118 /* ============================= */
119 /* Local Macros & Definitions */
120 --- a/src/drv_vmmc_init_cap.c
121 +++ b/src/drv_vmmc_init_cap.c
122 @@ -22,6 +22,11 @@
123 #include "drv_mps_vmmc.h"
124 #include "drv_mps_vmmc_device.h"
125
126 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
127 +# define IFX_MPS_CHIPID_VERSION_GET IFXMIPS_MPS_CHIPID_VERSION_GET
128 +# define IFX_MPS_CHIPID IFXMIPS_MPS_CHIPID
129 +#endif
130 +
131 /* ============================= */
132 /* Configuration defintions */
133 /* ============================= */
134 --- a/src/mps/drv_mps_vmmc_common.c
135 +++ b/src/mps/drv_mps_vmmc_common.c
136 @@ -17,6 +17,7 @@
137 /* Includes */
138 /* ============================= */
139 #include "drv_config.h"
140 +#include "drv_vmmc_init.h"
141
142 #undef USE_PLAIN_VOICE_FIRMWARE
143 #undef PRINT_ON_ERR_INTERRUPT
144 @@ -35,8 +36,35 @@
145 #include "ifxos_interrupt.h"
146 #include "ifxos_time.h"
147
148 -#include <asm/ifx/ifx_regs.h>
149 -#include <asm/ifx/ifx_gptu.h>
150 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
151 +# include <lantiq.h>
152 +# include <irq.h>
153 +# include <lantiq_timer.h>
154 +
155 +# define ifx_gptu_timer_request lq_request_timer
156 +# define ifx_gptu_timer_start lq_start_timer
157 +# define ifx_gptu_countvalue_get lq_get_count_value
158 +# define ifx_gptu_timer_free lq_free_timer
159 +
160 +# define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
161 +# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
162 +# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
163 +# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
164 +# define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR
165 +# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
166 +# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
167 +# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
168 +# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
169 +# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
170 +# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
171 +
172 +# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
173 +
174 +# define bsp_mask_and_ack_irq lq_mask_and_ack_irq
175 +#else
176 +# include <asm/ifx/ifx_regs.h>
177 +# include <asm/ifx/ifx_gptu.h>
178 +#endif
179
180 #include "drv_mps_vmmc.h"
181 #include "drv_mps_vmmc_dbg.h"
182 @@ -201,7 +229,8 @@
183 */
184 IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
185 {
186 - IFX_uint32_t ptr, flags;
187 + unsigned long flags;
188 + IFX_uint32_t ptr;
189 IFX_int32_t index = fastbuf_index;
190
191 if (fastbuf_initialized == 0)
192 @@ -255,7 +284,7 @@
193 */
194 IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
195 {
196 - IFX_uint32_t flags;
197 + unsigned long flags;
198 IFX_int32_t index = fastbuf_index;
199
200 IFXOS_LOCKINT (flags);
201 @@ -451,7 +480,7 @@
202 */
203 static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
204 {
205 - IFX_uint32_t flags;
206 + unsigned long flags;
207
208 if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
209 {
210 @@ -478,7 +507,7 @@
211 */
212 static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
213 {
214 - IFX_uint32_t flags;
215 + unsigned long flags;
216
217 if (mps_buffer.buf_level < value)
218 {
219 @@ -946,7 +975,7 @@
220 mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
221 IFX_boolean_t from_kernel)
222 {
223 - IFX_uint32_t flags;
224 + unsigned long flags;
225
226 IFXOS_LOCKINT (flags);
227
228 @@ -1062,7 +1091,7 @@
229 IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
230 {
231 IFX_int32_t count;
232 - IFX_uint32_t flags;
233 + unsigned long flags;
234
235 IFXOS_LOCKINT (flags);
236 IFXOS_BlockFree (pFW_img_data);
237 @@ -1558,7 +1587,7 @@
238 IFX_uint32_t * bytes)
239 {
240 IFX_int32_t i, ret;
241 - IFX_uint32_t flags;
242 + unsigned long flags;
243
244 IFXOS_LOCKINT (flags);
245
246 @@ -1768,7 +1797,7 @@
247 {
248 mps_fifo *mbx;
249 IFX_uint32_t i;
250 - IFX_uint32_t flags;
251 + unsigned long flags;
252 IFX_int32_t retval = -EAGAIN;
253 IFX_int32_t retries = 0;
254 IFX_uint32_t word = 0;
255 @@ -2163,6 +2192,7 @@
256 TRACE (MPS, DBG_LEVEL_HIGH,
257 ("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
258 }
259 +
260 return retval;
261 }
262
263 @@ -2186,7 +2216,7 @@
264 mps_mbx_dev *mbx_dev;
265 MbxMsg_s msg;
266 IFX_uint32_t bytes_read = 0;
267 - IFX_uint32_t flags;
268 + unsigned long flags;
269 IFX_int32_t ret;
270
271 /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
272 @@ -2277,7 +2307,7 @@
273 {
274 ifx_mps_bufman_dec_level (1);
275 if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
276 - (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
277 + ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
278 {
279 IFXOS_LockRelease (pMPSDev->provide_buffer);
280 }
281 @@ -2320,7 +2350,7 @@
282 #endif /* CONFIG_PROC_FS */
283 ifx_mps_bufman_dec_level (1);
284 if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
285 - (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
286 + ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
287 {
288 IFXOS_LockRelease (pMPSDev->provide_buffer);
289 }
290 @@ -2350,7 +2380,7 @@
291 IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
292 {
293 mps_fifo *mbx;
294 - IFX_uint32_t flags;
295 + unsigned long flags;
296
297 /* set pointer to upstream command mailbox */
298 mbx = &(pMPSDev->cmd_upstrm_fifo);
299 @@ -2398,7 +2428,7 @@
300 mps_event_msg msg;
301 IFX_int32_t length = 0;
302 IFX_int32_t read_length = 0;
303 - IFX_uint32_t flags;
304 + unsigned long flags;
305
306 /* set pointer to upstream event mailbox */
307 mbx = &(pMPSDev->event_upstrm_fifo);
308 @@ -2641,7 +2671,7 @@
309 */
310 IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
311 {
312 - IFX_uint32_t flags;
313 + unsigned long flags;
314 MPS_Ad0Reg_u Ad0Reg;
315
316 IFXOS_LOCKINT (flags);
317 @@ -2667,7 +2697,7 @@
318 */
319 IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
320 {
321 - IFX_uint32_t flags;
322 + unsigned long flags;
323 MPS_Ad0Reg_u Ad0Reg;
324
325 IFXOS_LOCKINT (flags);
326 @@ -2794,6 +2824,7 @@
327 }
328 }
329
330 +
331 if (MPS_Ad0StatusReg.fld.du_mbx)
332 {
333 #ifdef CONFIG_PROC_FS
334 @@ -3087,7 +3118,8 @@
335 */
336 IFX_return_t ifx_mps_init_gpt ()
337 {
338 - IFX_uint32_t flags, timer_flags, timer, loops = 0;
339 + unsigned long flags;
340 + IFX_uint32_t timer_flags, timer, loops = 0;
341 IFX_ulong_t count;
342 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
343 timer = TIMER1A;
344 --- a/src/mps/drv_mps_vmmc_danube.c
345 +++ b/src/mps/drv_mps_vmmc_danube.c
346 @@ -32,9 +32,21 @@
347 #include "ifxos_select.h"
348 #include "ifxos_interrupt.h"
349
350 -#include <asm/ifx/ifx_regs.h>
351 -#include <asm/ifx/ifx_gpio.h>
352 -#include <asm/ifx/common_routines.h>
353 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
354 +# include <lantiq.h>
355 +# include <irq.h>
356 +# include <lantiq_timer.h>
357 +# include <linux/dma-mapping.h>
358 +
359 +
360 +# define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
361 +#define IFX_RCU_RST_REQ_CPU1 (1 << 3)
362 +# define IFX_RCU_RST_REQ LQ_RCU_RST
363 +#else
364 +# include <asm/ifx/ifx_regs.h>
365 +# include <asm/ifx_vpe.h>
366 +# include <asm/ifx/ifx_gpio.h>
367 +#endif
368
369 #include "drv_mps_vmmc.h"
370 #include "drv_mps_vmmc_dbg.h"
371 @@ -71,6 +83,20 @@
372 /* Local function definition */
373 /* ============================= */
374
375 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
376 +IFX_uint32_t ifx_get_cp1_size(IFX_void_t)
377 +{
378 + return 2;
379 +}
380 +
381 +unsigned int *lq_get_cp1_base(void);
382 +
383 +IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)
384 +{
385 + return lq_get_cp1_base();
386 +}
387 +#endif
388 +
389 /******************************************************************************
390 * DANUBE Specific Routines
391 ******************************************************************************/
392 @@ -130,6 +156,15 @@
393 }
394
395 /* check if FW image fits in available memory space */
396 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
397 + if (mem > ifx_get_cp1_size()<<20)
398 + {
399 + TRACE (MPS, DBG_LEVEL_HIGH,
400 + ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
401 + __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));
402 + return IFX_ERROR;
403 + }
404 +#else
405 if (mem > ifx_get_cp1_size())
406 {
407 TRACE (MPS, DBG_LEVEL_HIGH,
408 @@ -137,6 +172,7 @@
409 __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
410 return IFX_ERROR;
411 }
412 +#endif
413
414 /* reset the driver */
415 ifx_mps_reset ();
416 @@ -357,7 +393,7 @@
417 */
418 IFX_void_t ifx_mps_wdog_expiry()
419 {
420 - IFX_uint32_t flags;
421 + unsigned long flags;
422
423 IFXOS_LOCKINT (flags);
424 /* recalculate and compare the firmware checksum */
425 --- a/src/mps/drv_mps_vmmc_device.h
426 +++ b/src/mps/drv_mps_vmmc_device.h
427 @@ -16,8 +16,15 @@
428 declarations.
429 *******************************************************************************/
430
431 -#include <asm/ifx/ifx_regs.h>
432 -#include <asm/ifx_vpe.h>
433 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
434 +# include <lantiq.h>
435 +# include <irq.h>
436 +# include <xway/xway.h>
437 +# include <gpio.h>
438 +#else
439 +# include <asm/ifx/ifx_regs.h>
440 +# include <asm/ifx_vpe.h>
441 +#endif
442
443 /* ============================= */
444 /* MPS Common defines */
445 --- a/src/mps/drv_mps_vmmc_linux.c
446 +++ b/src/mps/drv_mps_vmmc_linux.c
447 @@ -40,10 +40,28 @@
448 #include <linux/moduleparam.h>
449 #endif /* */
450
451 -
452 -#include <asm/ifx/irq.h>
453 -#include <asm/ifx/ifx_regs.h>
454 -#include <asm/ifx_vpe.h>
455 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
456 +#include "drv_vmmc_init.h"
457 +# include <lantiq.h>
458 +# include <irq.h>
459 +
460 +# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
461 +# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
462 +# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
463 +# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
464 +# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
465 +# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
466 +
467 +# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
468 +# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
469 +# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
470 +#define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
471 +# define IFX_ICU_IM4_IER (LQ_ICU_BASE_ADDR + 0x00A8)
472 +#else
473 +# include <asm/ifx/irq.h>
474 +# include <asm/ifx/ifx_regs.h>
475 +# include <asm/ifx_vpe.h>
476 +#endif
477
478 /* lib_ifxos headers */
479 #include "ifx_types.h"
480 @@ -915,7 +933,7 @@
481 #endif /* MPS_FIFO_BLOCKING_WRITE */
482 case FIO_MPS_GET_STATUS:
483 {
484 - IFX_uint32_t flags;
485 + unsigned long flags;
486
487 /* get the status of the channel */
488 if (!from_kernel)
489 @@ -949,7 +967,7 @@
490 #if CONFIG_MPS_HISTORY_SIZE > 0
491 case FIO_MPS_GET_CMD_HISTORY:
492 {
493 - IFX_uint32_t flags;
494 + unsigned long flags;
495
496 if (from_kernel)
497 {
498 @@ -1641,6 +1659,7 @@
499 sprintf (buf + len, " minLv: \t %8d\n",
500 ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
501 }
502 +
503 return len;
504 }
505
506 --- a/src/drv_vmmc_init.h
507 +++ b/src/drv_vmmc_init.h
508 @@ -53,4 +53,41 @@
509 extern IFX_int32_t VMMC_DeviceDriverStart(IFX_void_t);
510 extern IFX_void_t VMMC_DeviceDriverStop(IFX_void_t);
511
512 +
513 +#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
514 +#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
515 +
516 +#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
517 +#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
518 +#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
519 +#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
520 +#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
521 +#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
522 +#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
523 +#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
524 +#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
525 +#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
526 +#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
527 +#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
528 +#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
529 +#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
530 +#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
531 +#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
532 +#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
533 +#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
534 +#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
535 +#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
536 +#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
537 +#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
538 +#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
539 +#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
540 +#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
541 +
542 +#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
543 +#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28)
544 +#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
545 +#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)
546 +#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
547 +#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)
548 +
549 #endif /* _DRV_VMMC_INIT_H */
550 --- a/src/drv_vmmc_ioctl.c
551 +++ b/src/drv_vmmc_ioctl.c
552 @@ -18,6 +18,7 @@
553 /* Includes */
554 /* ============================= */
555 #include "drv_api.h"
556 +#include "drv_vmmc_init.h"
557 #include "drv_vmmc_api.h"
558 #include "drv_vmmc_bbd.h"
559
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