projects / openwrt / openwrt.git / blob
? search:


4ca06d6631d34aecf207287abc1515bb6b1dd28e
[openwrt/openwrt.git] / package / ubsec_ssb / src / ubsec_ssb.c
1 /* $Id: $ */
2
3 /*
4 * Copyright (c) 2008 Daniel Mueller (daniel@danm.de)
5 * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com)
6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Effort sponsored in part by the Defense Advanced Research Projects
32 * Agency (DARPA) and Air Force Research Laboratory, Air Force
33 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
34 *
35 */
36 #undef UBSEC_DEBUG
37 #undef UBSEC_VERBOSE_DEBUG
38
39 #ifdef UBSEC_VERBOSE_DEBUG
40 #define UBSEC_DEBUG
41 #endif
42
43 /*
44 * uBsec BCM5365 hardware crypto accelerator
45 */
46
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/moduleparam.h>
50 #include <linux/proc_fs.h>
51 #include <linux/types.h>
52 #include <linux/init.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/fs.h>
56 #include <linux/random.h>
57 #include <linux/skbuff.h>
58 #include <linux/stat.h>
59 #include <asm/io.h>
60
61 #include <linux/ssb/ssb.h>
62
63 /*
64 * BSD queue
65 */
66 #include "bsdqueue.h"
67
68 /*
69 * OCF
70 */
71 #include "cryptodev.h"
72 #include "uio.h"
73
74 #define HMAC_HACK 1
75
76 #ifdef HMAC_HACK
77 #include "hmachack.h"
78 #include "md5.h"
79 #include "md5.c"
80 #include "sha1.h"
81 #include "sha1.c"
82 #endif
83
84 #include "ubsecreg.h"
85 #include "ubsecvar.h"
86
87 #define DRV_MODULE_NAME "ubsec_ssb"
88 #define PFX DRV_MODULE_NAME ": "
89 #define DRV_MODULE_VERSION "0.02"
90 #define DRV_MODULE_RELDATE "Feb 21, 2009"
91
92 #if 1
93 #define DPRINTF(a...) \
94 if (debug) \
95 { \
96 printk(DRV_MODULE_NAME ": " a); \
97 }
98 #else
99 #define DPRINTF(a...)
100 #endif
101
102 /*
103 * Prototypes
104 */
105 static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *);
106 static int __devinit ubsec_ssb_probe(struct ssb_device *sdev,
107 const struct ssb_device_id *ent);
108 static void __devexit ubsec_ssb_remove(struct ssb_device *sdev);
109 int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent,
110 struct device *self);
111 static void ubsec_setup_mackey(struct ubsec_session *ses, int algo,
112 caddr_t key, int klen);
113 static int dma_map_skb(struct ubsec_softc *sc,
114 struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen);
115 static int dma_map_uio(struct ubsec_softc *sc,
116 struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen);
117 static void dma_unmap(struct ubsec_softc *sc,
118 struct ubsec_dma_alloc *q_map, int mlen);
119 static int ubsec_dmamap_aligned(struct ubsec_softc *sc,
120 const struct ubsec_dma_alloc *q_map, int mlen);
121
122 #ifdef UBSEC_DEBUG
123 static int proc_read(char *buf, char **start, off_t offset,
124 int size, int *peof, void *data);
125 #endif
126
127 void ubsec_reset_board(struct ubsec_softc *);
128 void ubsec_init_board(struct ubsec_softc *);
129 void ubsec_cleanchip(struct ubsec_softc *);
130 void ubsec_totalreset(struct ubsec_softc *);
131 int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *);
132
133 static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
134 static int ubsec_freesession(device_t, u_int64_t);
135 static int ubsec_process(device_t, struct cryptop *, int);
136
137 void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
138 void ubsec_feed(struct ubsec_softc *);
139 void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int);
140 void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
141 int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *,
142 size_t, int);
143
144 /* DEBUG crap... */
145 void ubsec_dump_pb(struct ubsec_pktbuf *);
146 void ubsec_dump_mcr(struct ubsec_mcr *);
147
148 #define READ_REG(sc,r) \
149 ssb_read32((sc)->sdev, (r));
150 #define WRITE_REG(sc,r,val) \
151 ssb_write32((sc)->sdev, (r), (val));
152 #define READ_REG_SDEV(sdev,r) \
153 ssb_read32((sdev), (r));
154 #define WRITE_REG_SDEV(sdev,r,val) \
155 ssb_write32((sdev), (r), (val));
156
157 #define SWAP32(x) (x) = htole32(ntohl((x)))
158 #define HTOLE32(x) (x) = htole32(x)
159
160 #ifdef __LITTLE_ENDIAN
161 #define letoh16(x) (x)
162 #define letoh32(x) (x)
163 #endif
164
165 static int debug;
166 module_param(debug, int, 0644);
167 MODULE_PARM_DESC(debug, "Enable debug output");
168
169 #define UBSEC_SSB_MAX_CHIPS 1
170 static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS];
171 static struct ubsec_stats ubsecstats;
172
173 #ifdef UBSEC_DEBUG
174 static struct proc_dir_entry *procdebug;
175 #endif
176
177 static struct ssb_device_id ubsec_ssb_tbl[] = {
178 /* Broadcom BCM5365P IPSec Core */
179 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV),
180 SSB_DEVTABLE_END
181 };
182
183 static struct ssb_driver ubsec_ssb_driver = {
184 .name = DRV_MODULE_NAME,
185 .id_table = ubsec_ssb_tbl,
186 .probe = ubsec_ssb_probe,
187 .remove = __devexit_p(ubsec_ssb_remove),
188 /*
189 .suspend = ubsec_ssb_suspend,
190 .resume = ubsec_ssb_resume
191 */
192 };
193
194 static device_method_t ubsec_ssb_methods = {
195 /* crypto device methods */
196 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
197 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
198 DEVMETHOD(cryptodev_process, ubsec_process),
199 };
200
201 #ifdef UBSEC_DEBUG
202 static int
203 proc_read(char *buf, char **start, off_t offset,
204 int size, int *peof, void *data)
205 {
206 int i = 0, byteswritten = 0, ret;
207 unsigned int stat, ctrl;
208 #ifdef UBSEC_VERBOSE_DEBUG
209 struct ubsec_q *q;
210 struct ubsec_dma *dmap;
211 #endif
212
213 while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL))
214 {
215 struct ubsec_softc *sc = ubsec_chip_idx[i];
216
217 stat = READ_REG(sc, BS_STAT);
218 ctrl = READ_REG(sc, BS_CTRL);
219 ret = snprintf((buf + byteswritten),
220 (size - byteswritten) ,
221 "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl);
222
223 byteswritten += ret;
224
225 #ifdef UBSEC_VERBOSE_DEBUG
226 printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl);
227
228 /* Dump all queues MCRs */
229 if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
230 BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next)
231 {
232 dmap = q->q_dma;
233 ubsec_dump_mcr(&dmap->d_dma->d_mcr);
234 }
235 }
236 #endif
237
238 i++;
239 }
240
241 *peof = 1;
242
243 return byteswritten;
244 }
245 #endif
246
247 /*
248 * map in a given sk_buff
249 */
250 static int
251 dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen)
252 {
253 int i = 0;
254 dma_addr_t tmp;
255
256 #ifdef UBSEC_DEBUG
257 DPRINTF("%s()\n", __FUNCTION__);
258 #endif
259
260 /*
261 * We support only a limited number of fragments.
262 */
263 if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER))
264 {
265 printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER);
266 return (-ENOMEM);
267 }
268
269 #ifdef UBSEC_VERBOSE_DEBUG
270 DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb));
271 #endif
272
273 /* first data package */
274 tmp = dma_map_single(sc->sc_dv,
275 skb->data,
276 skb_headlen(skb),
277 DMA_BIDIRECTIONAL);
278
279 q_map[i].dma_paddr = tmp;
280 q_map[i].dma_vaddr = skb->data;
281 q_map[i].dma_size = skb_headlen(skb);
282
283 if (unlikely(tmp == 0))
284 {
285 printk(KERN_ERR "Could not map memory region for dma.\n");
286 return (-EINVAL);
287 }
288
289 #ifdef UBSEC_VERBOSE_DEBUG
290 DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp);
291 #endif
292
293
294 /* all other data packages */
295 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
296
297 #ifdef UBSEC_VERBOSE_DEBUG
298 DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1,
299 (unsigned int)page_address(skb_shinfo(skb)->frags[i].page) +
300 skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size);
301 #endif
302
303 tmp = dma_map_single(sc->sc_dv,
304 page_address(skb_shinfo(skb)->frags[i].page) +
305 skb_shinfo(skb)->frags[i].page_offset,
306 skb_shinfo(skb)->frags[i].size,
307 DMA_BIDIRECTIONAL);
308
309 q_map[i + 1].dma_paddr = tmp;
310 q_map[i + 1].dma_vaddr = (void*)(page_address(skb_shinfo(skb)->frags[i].page) +
311 skb_shinfo(skb)->frags[i].page_offset);
312 q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size;
313
314 if (unlikely(tmp == 0))
315 {
316 printk(KERN_ERR "Could not map memory region for dma.\n");
317 return (-EINVAL);
318 }
319
320 #ifdef UBSEC_VERBOSE_DEBUG
321 DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp);
322 #endif
323
324 }
325 *mlen = i + 1;
326
327 return(0);
328 }
329
330 /*
331 * map in a given uio buffer
332 */
333
334 static int
335 dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen)
336 {
337 struct iovec *iov = uio->uio_iov;
338 int n;
339 dma_addr_t tmp;
340
341 #ifdef UBSEC_DEBUG
342 DPRINTF("%s()\n", __FUNCTION__);
343 #endif
344
345 /*
346 * We support only a limited number of fragments.
347 */
348 if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER))
349 {
350 printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER);
351 return (-ENOMEM);
352 }
353
354 for (n = 0; n < uio->uio_iovcnt; n++) {
355 #ifdef UBSEC_VERBOSE_DEBUG
356 DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len);
357 #endif
358 tmp = dma_map_single(sc->sc_dv,
359 iov->iov_base,
360 iov->iov_len,
361 DMA_BIDIRECTIONAL);
362
363 q_map[n].dma_paddr = tmp;
364 q_map[n].dma_vaddr = iov->iov_base;
365 q_map[n].dma_size = iov->iov_len;
366
367 if (unlikely(tmp == 0))
368 {
369 printk(KERN_ERR "Could not map memory region for dma.\n");
370 return (-EINVAL);
371 }
372
373 #ifdef UBSEC_VERBOSE_DEBUG
374 DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp);
375 #endif
376
377 iov++;
378 }
379 *mlen = n;
380
381 return(0);
382 }
383
384 static void
385 dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen)
386 {
387 int i;
388
389 #ifdef UBSEC_DEBUG
390 DPRINTF("%s()\n", __FUNCTION__);
391 #endif
392
393 for(i = 0; i < mlen; i++)
394 {
395 #ifdef UBSEC_VERBOSE_DEBUG
396 DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size);
397 #endif
398 dma_unmap_single(sc->sc_dv,
399 q_map[i].dma_paddr,
400 q_map[i].dma_size,
401 DMA_BIDIRECTIONAL);
402 }
403 return;
404 }
405
406 /*
407 * Is the operand suitable aligned for direct DMA. Each
408 * segment must be aligned on a 32-bit boundary and all
409 * but the last segment must be a multiple of 4 bytes.
410 */
411 static int
412 ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen)
413 {
414 int i;
415
416 #ifdef UBSEC_DEBUG
417 DPRINTF("%s()\n", __FUNCTION__);
418 #endif
419
420 for (i = 0; i < mlen; i++) {
421 if (q_map[i].dma_paddr & 3)
422 return (0);
423 if (i != (mlen - 1) && (q_map[i].dma_size & 3))
424 return (0);
425 }
426 return (1);
427 }
428
429
430 #define N(a) (sizeof(a) / sizeof (a[0]))
431 static void
432 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
433 {
434 #ifdef HMAC_HACK
435 MD5_CTX md5ctx;
436 SHA1_CTX sha1ctx;
437 int i;
438
439 #ifdef UBSEC_DEBUG
440 DPRINTF("%s()\n", __FUNCTION__);
441 #endif
442
443 for (i = 0; i < klen; i++)
444 key[i] ^= HMAC_IPAD_VAL;
445
446 if (algo == CRYPTO_MD5_HMAC) {
447 MD5Init(&md5ctx);
448 MD5Update(&md5ctx, key, klen);
449 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
450 bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8));
451 } else {
452 SHA1Init(&sha1ctx);
453 SHA1Update(&sha1ctx, key, klen);
454 SHA1Update(&sha1ctx, hmac_ipad_buffer,
455 SHA1_HMAC_BLOCK_LEN - klen);
456 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
457 }
458
459 for (i = 0; i < klen; i++)
460 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
461
462 if (algo == CRYPTO_MD5_HMAC) {
463 MD5Init(&md5ctx);
464 MD5Update(&md5ctx, key, klen);
465 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
466 bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8));
467 } else {
468 SHA1Init(&sha1ctx);
469 SHA1Update(&sha1ctx, key, klen);
470 SHA1Update(&sha1ctx, hmac_opad_buffer,
471 SHA1_HMAC_BLOCK_LEN - klen);
472 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
473 }
474
475 for (i = 0; i < klen; i++)
476 key[i] ^= HMAC_OPAD_VAL;
477
478 #else /* HMAC_HACK */
479 DPRINTF("md5/sha not implemented\n");
480 #endif /* HMAC_HACK */
481 }
482 #undef N
483
484 static int
485 __devinit ubsec_ssb_probe(struct ssb_device *sdev,
486 const struct ssb_device_id *ent)
487 {
488 int err;
489
490 #ifdef UBSEC_DEBUG
491 DPRINTF("%s()\n", __FUNCTION__);
492 #endif
493
494 err = ssb_bus_powerup(sdev->bus, 0);
495 if (err) {
496 dev_err(sdev->dev, "Failed to powerup the bus\n");
497 goto err_powerup;
498 }
499
500 err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr,
501 IRQF_DISABLED | IRQF_SHARED, DRV_MODULE_NAME, sdev);
502 if (err) {
503 dev_err(sdev->dev, "Could not request irq\n");
504 goto err_out_powerdown;
505 }
506
507 err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK);
508 if (err) {
509 dev_err(sdev->dev,
510 "Required 32BIT DMA mask unsupported by the system.\n");
511 goto err_out_powerdown;
512 }
513
514 printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n",
515 sdev->irq);
516
517 DPRINTF("Vendor: %x, core id: %x, revision: %x\n",
518 sdev->id.vendor, sdev->id.coreid, sdev->id.revision);
519
520 ssb_device_enable(sdev, 0);
521
522 if (ubsec_attach(sdev, ent, sdev->dev) != 0)
523 goto err_disable_interrupt;
524
525 #ifdef UBSEC_DEBUG
526 procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL);
527 if (procdebug)
528 {
529 procdebug->read_proc = proc_read;
530 procdebug->data = NULL;
531 } else
532 DPRINTF("Unable to create proc file.\n");
533 #endif
534
535 return 0;
536
537 err_disable_interrupt:
538 free_irq(sdev->irq, sdev);
539
540 err_out_powerdown:
541 ssb_bus_may_powerdown(sdev->bus);
542
543 err_powerup:
544 ssb_device_disable(sdev, 0);
545 return err;
546 }
547
548 static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) {
549
550 struct ubsec_softc *sc;
551 unsigned int ctrlflgs;
552 struct ubsec_dma *dmap;
553 u_int32_t i;
554
555 #ifdef UBSEC_DEBUG
556 DPRINTF("%s()\n", __FUNCTION__);
557 #endif
558
559 ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL);
560 /* disable all IPSec Core interrupts globally */
561 ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT |
562 BS_CTRL_DMAERR);
563 WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs);
564
565 free_irq(sdev->irq, sdev);
566
567 sc = (struct ubsec_softc *)ssb_get_drvdata(sdev);
568
569 /* unregister all crypto algorithms */
570 crypto_unregister_all(sc->sc_cid);
571
572 /* Free queue / dma memory */
573 for (i = 0; i < UBS_MAX_NQUEUE; i++) {
574 struct ubsec_q *q;
575
576 q = sc->sc_queuea[i];
577 if (q != NULL)
578 {
579 dmap = q->q_dma;
580 if (dmap != NULL)
581 {
582 ubsec_dma_free(sc, &dmap->d_alloc);
583 q->q_dma = NULL;
584 }
585 kfree(q);
586 }
587 sc->sc_queuea[i] = NULL;
588 }
589
590 ssb_bus_may_powerdown(sdev->bus);
591 ssb_device_disable(sdev, 0);
592 ssb_set_drvdata(sdev, NULL);
593
594 #ifdef UBSEC_DEBUG
595 if (procdebug)
596 remove_proc_entry(DRV_MODULE_NAME, NULL);
597 #endif
598
599 }
600
601
602 int
603 ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent,
604 struct device *self)
605 {
606 struct ubsec_softc *sc = NULL;
607 struct ubsec_dma *dmap;
608 u_int32_t i;
609 static int num_chips = 0;
610
611 #ifdef UBSEC_DEBUG
612 DPRINTF("%s()\n", __FUNCTION__);
613 #endif
614
615 sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL);
616 if (!sc)
617 return(-ENOMEM);
618 memset(sc, 0, sizeof(*sc));
619
620 sc->sc_dv = sdev->dev;
621 sc->sdev = sdev;
622
623 spin_lock_init(&sc->sc_ringmtx);
624
625 softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods);
626
627 /* Maybe someday there are boards with more than one chip available */
628 if (num_chips < UBSEC_SSB_MAX_CHIPS) {
629 ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc;
630 num_chips++;
631 }
632
633 ssb_set_drvdata(sdev, sc);
634
635 BSD_SIMPLEQ_INIT(&sc->sc_queue);
636 BSD_SIMPLEQ_INIT(&sc->sc_qchip);
637 BSD_SIMPLEQ_INIT(&sc->sc_queue2);
638 BSD_SIMPLEQ_INIT(&sc->sc_qchip2);
639 BSD_SIMPLEQ_INIT(&sc->sc_q2free);
640
641 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
642
643 sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE);
644 if (sc->sc_cid < 0) {
645 device_printf(sc->sc_dev, "could not get crypto driver id\n");
646 return -1;
647 }
648
649 BSD_SIMPLEQ_INIT(&sc->sc_freequeue);
650 dmap = sc->sc_dmaa;
651 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
652 struct ubsec_q *q;
653
654 q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL);
655 if (q == NULL) {
656 printf(": can't allocate queue buffers\n");
657 break;
658 }
659
660 if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) {
661 printf(": can't allocate dma buffers\n");
662 kfree(q);
663 break;
664 }
665 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
666
667 q->q_dma = dmap;
668 sc->sc_queuea[i] = q;
669
670 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
671 }
672
673 /*
674 * Reset Broadcom chip
675 */
676 ubsec_reset_board(sc);
677
678 /*
679 * Init Broadcom chip
680 */
681 ubsec_init_board(sc);
682
683 /* supported crypto algorithms */
684 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
685 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
686
687 if (sc->sc_flags & UBS_FLAGS_AES) {
688 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
689 printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n");
690 }
691 else
692 printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n");
693
694 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
695 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
696
697 return 0;
698 }
699
700 /*
701 * UBSEC Interrupt routine
702 */
703 static irqreturn_t
704 ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs)
705 {
706 struct ubsec_softc *sc = NULL;
707 volatile u_int32_t stat;
708 struct ubsec_q *q;
709 struct ubsec_dma *dmap;
710 int npkts = 0, i;
711
712 #ifdef UBSEC_VERBOSE_DEBUG
713 DPRINTF("%s()\n", __FUNCTION__);
714 #endif
715
716 sc = (struct ubsec_softc *)ssb_get_drvdata(arg);
717
718 stat = READ_REG(sc, BS_STAT);
719
720 stat &= sc->sc_statmask;
721 if (stat == 0)
722 return IRQ_NONE;
723
724 WRITE_REG(sc, BS_STAT, stat); /* IACK */
725
726 /*
727 * Check to see if we have any packets waiting for us
728 */
729 if ((stat & BS_STAT_MCR1_DONE)) {
730 while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
731 q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip);
732 dmap = q->q_dma;
733
734 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
735 {
736 DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags);
737 break;
738 }
739
740 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
741
742 npkts = q->q_nstacked_mcrs;
743 /*
744 * search for further sc_qchip ubsec_q's that share
745 * the same MCR, and complete them too, they must be
746 * at the top.
747 */
748 for (i = 0; i < npkts; i++) {
749 if(q->q_stacked_mcr[i])
750 ubsec_callback(sc, q->q_stacked_mcr[i]);
751 else
752 break;
753 }
754 ubsec_callback(sc, q);
755 }
756
757 /*
758 * Don't send any more packet to chip if there has been
759 * a DMAERR.
760 */
761 if (likely(!(stat & BS_STAT_DMAERR)))
762 ubsec_feed(sc);
763 else
764 DPRINTF("DMA error occurred. Stop feeding crypto chip.\n");
765 }
766
767 /*
768 * Check to see if we got any DMA Error
769 */
770 if (stat & BS_STAT_DMAERR) {
771 volatile u_int32_t a = READ_REG(sc, BS_ERR);
772
773 printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME,
774 (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR);
775
776 ubsecstats.hst_dmaerr++;
777 ubsec_totalreset(sc);
778 ubsec_feed(sc);
779 }
780
781 return IRQ_HANDLED;
782 }
783
784 /*
785 * ubsec_feed() - aggregate and post requests to chip
786 * It is assumed that the caller set splnet()
787 */
788 void
789 ubsec_feed(struct ubsec_softc *sc)
790 {
791 #ifdef UBSEC_VERBOSE_DEBUG
792 static int max;
793 #endif
794 struct ubsec_q *q, *q2;
795 int npkts, i;
796 void *v;
797 u_int32_t stat;
798
799 npkts = sc->sc_nqueue;
800 if (npkts > UBS_MAX_AGGR)
801 npkts = UBS_MAX_AGGR;
802 if (npkts < 2)
803 goto feed1;
804
805 stat = READ_REG(sc, BS_STAT);
806
807 if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
808 if(stat & BS_STAT_DMAERR) {
809 ubsec_totalreset(sc);
810 ubsecstats.hst_dmaerr++;
811 }
812 return;
813 }
814
815 #ifdef UBSEC_VERBOSE_DEBUG
816 DPRINTF("merging %d records\n", npkts);
817
818 /* XXX temporary aggregation statistics reporting code */
819 if (max < npkts) {
820 max = npkts;
821 DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max);
822 }
823 #endif /* UBSEC_VERBOSE_DEBUG */
824
825 q = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
826 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
827 --sc->sc_nqueue;
828
829 #if 0
830 /*
831 * XXX
832 * We use dma_map_single() - no sync required!
833 */
834
835 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
836 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
837 if (q->q_dst_map != NULL)
838 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
839 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
840 #endif
841
842 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
843
844 for (i = 0; i < q->q_nstacked_mcrs; i++) {
845 q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
846
847 #if 0
848 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
849 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
850 if (q2->q_dst_map != NULL)
851 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
852 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
853 #endif
854 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
855 --sc->sc_nqueue;
856
857 v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
858 sizeof(struct ubsec_mcr_add);
859 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
860 q->q_stacked_mcr[i] = q2;
861 }
862 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
863 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
864 #if 0
865 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
866 0, q->q_dma->d_alloc.dma_map->dm_mapsize,
867 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
868 #endif
869 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
870 offsetof(struct ubsec_dmachunk, d_mcr));
871 #ifdef UBSEC_VERBOSE_DEBUG
872 DPRINTF("feed (1): q->chip %p %08x %08x\n", q,
873 (u_int32_t)q->q_dma->d_alloc.dma_paddr,
874 (u_int32_t)(q->q_dma->d_alloc.dma_paddr +
875 offsetof(struct ubsec_dmachunk, d_mcr)));
876 #endif /* UBSEC_DEBUG */
877 return;
878
879 feed1:
880 while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) {
881 stat = READ_REG(sc, BS_STAT);
882
883 if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
884 if(stat & BS_STAT_DMAERR) {
885 ubsec_totalreset(sc);
886 ubsecstats.hst_dmaerr++;
887 }
888 break;
889 }
890
891 q = BSD_SIMPLEQ_FIRST(&sc->sc_queue);
892
893 #if 0
894 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
895 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
896 if (q->q_dst_map != NULL)
897 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
898 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
899 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
900 0, q->q_dma->d_alloc.dma_map->dm_mapsize,
901 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
902 #endif
903
904 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
905 offsetof(struct ubsec_dmachunk, d_mcr));
906 #ifdef UBSEC_VERBOSE_DEBUG
907 DPRINTF("feed (2): q->chip %p %08x %08x\n", q,
908 (u_int32_t)q->q_dma->d_alloc.dma_paddr,
909 (u_int32_t)(q->q_dma->d_alloc.dma_paddr +
910 offsetof(struct ubsec_dmachunk, d_mcr)));
911 #endif /* UBSEC_DEBUG */
912 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
913 --sc->sc_nqueue;
914 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
915 }
916 }
917
918 /*
919 * Allocate a new 'session' and return an encoded session id. 'sidp'
920 * contains our registration id, and should contain an encoded session
921 * id on successful allocation.
922 */
923 static int
924 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
925 {
926 struct cryptoini *c, *encini = NULL, *macini = NULL;
927 struct ubsec_softc *sc = NULL;
928 struct ubsec_session *ses = NULL;
929 int sesn, i;
930
931 #ifdef UBSEC_DEBUG
932 DPRINTF("%s()\n", __FUNCTION__);
933 #endif
934
935 if (sidp == NULL || cri == NULL)
936 return (EINVAL);
937
938 sc = device_get_softc(dev);
939
940 if (sc == NULL)
941 return (EINVAL);
942
943 for (c = cri; c != NULL; c = c->cri_next) {
944 if (c->cri_alg == CRYPTO_MD5_HMAC ||
945 c->cri_alg == CRYPTO_SHA1_HMAC) {
946 if (macini)
947 return (EINVAL);
948 macini = c;
949 } else if (c->cri_alg == CRYPTO_DES_CBC ||
950 c->cri_alg == CRYPTO_3DES_CBC ||
951 c->cri_alg == CRYPTO_AES_CBC) {
952 if (encini)
953 return (EINVAL);
954 encini = c;
955 } else
956 return (EINVAL);
957 }
958 if (encini == NULL && macini == NULL)
959 return (EINVAL);
960
961 if (sc->sc_sessions == NULL) {
962 ses = sc->sc_sessions = (struct ubsec_session *)kmalloc(
963 sizeof(struct ubsec_session), SLAB_ATOMIC);
964 if (ses == NULL)
965 return (ENOMEM);
966 memset(ses, 0, sizeof(struct ubsec_session));
967 sesn = 0;
968 sc->sc_nsessions = 1;
969 } else {
970 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
971 if (sc->sc_sessions[sesn].ses_used == 0) {
972 ses = &sc->sc_sessions[sesn];
973 break;
974 }
975 }
976
977 if (ses == NULL) {
978 sesn = sc->sc_nsessions;
979 ses = (struct ubsec_session *)kmalloc((sesn + 1) *
980 sizeof(struct ubsec_session), SLAB_ATOMIC);
981 if (ses == NULL)
982 return (ENOMEM);
983 memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session));
984 bcopy(sc->sc_sessions, ses, sesn *
985 sizeof(struct ubsec_session));
986 bzero(sc->sc_sessions, sesn *
987 sizeof(struct ubsec_session));
988 kfree(sc->sc_sessions);
989 sc->sc_sessions = ses;
990 ses = &sc->sc_sessions[sesn];
991 sc->sc_nsessions++;
992 }
993 }
994
995 bzero(ses, sizeof(struct ubsec_session));
996 ses->ses_used = 1;
997 if (encini) {
998 /* get an IV */
999 /* XXX may read fewer than requested */
1000 read_random(ses->ses_iv, sizeof(ses->ses_iv));
1001
1002 /* Go ahead and compute key in ubsec's byte order */
1003 if (encini->cri_alg == CRYPTO_DES_CBC) {
1004 /* DES uses the same key three times:
1005 * 1st encrypt -> 2nd decrypt -> 3nd encrypt */
1006 bcopy(encini->cri_key, &ses->ses_key[0], 8);
1007 bcopy(encini->cri_key, &ses->ses_key[2], 8);
1008 bcopy(encini->cri_key, &ses->ses_key[4], 8);
1009 ses->ses_keysize = 192; /* Fake! Actually its only 64bits ..
1010 oh no it is even less: 54bits. */
1011 } else if(encini->cri_alg == CRYPTO_3DES_CBC) {
1012 bcopy(encini->cri_key, ses->ses_key, 24);
1013 ses->ses_keysize = 192;
1014 } else if(encini->cri_alg == CRYPTO_AES_CBC) {
1015 ses->ses_keysize = encini->cri_klen;
1016
1017 if (ses->ses_keysize != 128 &&
1018 ses->ses_keysize != 192 &&
1019 ses->ses_keysize != 256)
1020 {
1021 DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize);
1022 return (EINVAL);
1023 }
1024 bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8));
1025 }
1026
1027 /* Hardware requires the keys in little endian byte order */
1028 for (i=0; i < (ses->ses_keysize / 32); i++)
1029 SWAP32(ses->ses_key[i]);
1030 }
1031
1032 if (macini) {
1033 ses->ses_mlen = macini->cri_mlen;
1034
1035 if (ses->ses_mlen == 0 ||
1036 ses->ses_mlen > SHA1_HASH_LEN) {
1037
1038 if (macini->cri_alg == CRYPTO_MD5_HMAC ||
1039 macini->cri_alg == CRYPTO_SHA1_HMAC)
1040 {
1041 ses->ses_mlen = DEFAULT_HMAC_LEN;
1042 } else
1043 {
1044 /*
1045 * Reserved for future usage. MD5/SHA1 calculations have
1046 * different hash sizes.
1047 */
1048 printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen);
1049 return (EINVAL);
1050 }
1051
1052 }
1053
1054 if (macini->cri_key != NULL) {
1055 ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key,
1056 macini->cri_klen / 8);
1057 }
1058 }
1059
1060 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
1061 return (0);
1062 }
1063
1064 /*
1065 * Deallocate a session.
1066 */
1067 static int
1068 ubsec_freesession(device_t dev, u_int64_t tid)
1069 {
1070 struct ubsec_softc *sc = device_get_softc(dev);
1071 int session;
1072 u_int32_t sid = ((u_int32_t)tid) & 0xffffffff;
1073
1074 #ifdef UBSEC_DEBUG
1075 DPRINTF("%s()\n", __FUNCTION__);
1076 #endif
1077
1078 if (sc == NULL)
1079 return (EINVAL);
1080
1081 session = UBSEC_SESSION(sid);
1082 if (session < sc->sc_nsessions) {
1083 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
1084 return (0);
1085 } else
1086 return (EINVAL);
1087 }
1088
1089 static int
1090 ubsec_process(device_t dev, struct cryptop *crp, int hint)
1091 {
1092 struct ubsec_q *q = NULL;
1093 int err = 0, i, j, nicealign;
1094 struct ubsec_softc *sc = device_get_softc(dev);
1095 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1096 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1097 int sskip, dskip, stheend, dtheend, ivsize = 8;
1098 int16_t coffset;
1099 struct ubsec_session *ses;
1100 struct ubsec_generic_ctx ctx;
1101 struct ubsec_dma *dmap = NULL;
1102 unsigned long flags;
1103
1104 #ifdef UBSEC_DEBUG
1105 DPRINTF("%s()\n", __FUNCTION__);
1106 #endif
1107
1108 if (unlikely(crp == NULL || crp->crp_callback == NULL)) {
1109 ubsecstats.hst_invalid++;
1110 return (EINVAL);
1111 }
1112
1113 if (unlikely(sc == NULL))
1114 return (EINVAL);
1115
1116 #ifdef UBSEC_VERBOSE_DEBUG
1117 DPRINTF("spin_lock_irqsave\n");
1118 #endif
1119 spin_lock_irqsave(&sc->sc_ringmtx, flags);
1120 //spin_lock_irq(&sc->sc_ringmtx);
1121
1122 if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1123 ubsecstats.hst_queuefull++;
1124 #ifdef UBSEC_VERBOSE_DEBUG
1125 DPRINTF("spin_unlock_irqrestore\n");
1126 #endif
1127 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1128 //spin_unlock_irq(&sc->sc_ringmtx);
1129 err = ENOMEM;
1130 goto errout2;
1131 }
1132
1133 q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue);
1134 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1135 #ifdef UBSEC_VERBOSE_DEBUG
1136 DPRINTF("spin_unlock_irqrestore\n");
1137 #endif
1138 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1139 //spin_unlock_irq(&sc->sc_ringmtx);
1140
1141 dmap = q->q_dma; /* Save dma pointer */
1142 bzero(q, sizeof(struct ubsec_q));
1143 bzero(&ctx, sizeof(ctx));
1144
1145 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1146 q->q_dma = dmap;
1147 ses = &sc->sc_sessions[q->q_sesn];
1148
1149 if (crp->crp_flags & CRYPTO_F_SKBUF) {
1150 q->q_src_m = (struct sk_buff *)crp->crp_buf;
1151 q->q_dst_m = (struct sk_buff *)crp->crp_buf;
1152 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1153 q->q_src_io = (struct uio *)crp->crp_buf;
1154 q->q_dst_io = (struct uio *)crp->crp_buf;
1155 } else {
1156 err = EINVAL;
1157 goto errout; /* XXX we don't handle contiguous blocks! */
1158 }
1159
1160 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1161
1162 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1163 dmap->d_dma->d_mcr.mcr_flags = 0;
1164 q->q_crp = crp;
1165
1166 crd1 = crp->crp_desc;
1167 if (crd1 == NULL) {
1168 err = EINVAL;
1169 goto errout;
1170 }
1171 crd2 = crd1->crd_next;
1172
1173 if (crd2 == NULL) {
1174 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1175 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1176 maccrd = crd1;
1177 enccrd = NULL;
1178 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1179 crd1->crd_alg == CRYPTO_3DES_CBC ||
1180 crd1->crd_alg == CRYPTO_AES_CBC) {
1181 maccrd = NULL;
1182 enccrd = crd1;
1183 } else {
1184 err = EINVAL;
1185 goto errout;
1186 }
1187 } else {
1188 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1189 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1190 (crd2->crd_alg == CRYPTO_DES_CBC ||
1191 crd2->crd_alg == CRYPTO_3DES_CBC ||
1192 crd2->crd_alg == CRYPTO_AES_CBC) &&
1193 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1194 maccrd = crd1;
1195 enccrd = crd2;
1196 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1197 crd1->crd_alg == CRYPTO_3DES_CBC ||
1198 crd1->crd_alg == CRYPTO_AES_CBC) &&
1199 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1200 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1201 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1202 enccrd = crd1;
1203 maccrd = crd2;
1204 } else {
1205 /*
1206 * We cannot order the ubsec as requested
1207 */
1208 printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n");
1209 err = EINVAL;
1210 goto errout;
1211 }
1212 }
1213
1214 /* Encryption/Decryption requested */
1215 if (enccrd) {
1216 encoffset = enccrd->crd_skip;
1217
1218 if (enccrd->crd_alg == CRYPTO_DES_CBC ||
1219 enccrd->crd_alg == CRYPTO_3DES_CBC)
1220 {
1221 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1222 ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES);
1223 ivsize = 8; /* [3]DES uses 64bit IVs */
1224 } else {
1225 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES);
1226 ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES);
1227 ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */
1228
1229 switch(ses->ses_keysize)
1230 {
1231 case 128:
1232 ctx.pc_flags |= htole16(UBS_PKTCTX_AES128);
1233 break;
1234 case 192:
1235 ctx.pc_flags |= htole16(UBS_PKTCTX_AES192);
1236 break;
1237 case 256:
1238 ctx.pc_flags |= htole16(UBS_PKTCTX_AES256);
1239 break;
1240 default:
1241 DPRINTF("invalid AES key size: %d\n", ses->ses_keysize);
1242 err = EINVAL;
1243 goto errout;
1244 }
1245 }
1246
1247 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1248 /* Direction: Outbound */
1249
1250 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1251
1252 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
1253 bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize);
1254 } else {
1255 for(i=0; i < (ivsize / 4); i++)
1256 ctx.pc_iv[i] = ses->ses_iv[i];
1257 }
1258
1259 /* If there is no IV in the buffer -> copy it here */
1260 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1261 if (crp->crp_flags & CRYPTO_F_SKBUF)
1262 /*
1263 m_copyback(q->q_src_m,
1264 enccrd->crd_inject,
1265 8, ctx.pc_iv);
1266 */
1267 crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m,
1268 enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv);
1269 else if (crp->crp_flags & CRYPTO_F_IOV)
1270 /*
1271 cuio_copyback(q->q_src_io,
1272 enccrd->crd_inject,
1273 8, ctx.pc_iv);
1274 */
1275 crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io,
1276 enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv);
1277 }
1278 } else {
1279 /* Direction: Inbound */
1280
1281 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1282
1283 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1284 bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize);
1285 else if (crp->crp_flags & CRYPTO_F_SKBUF)
1286 /*
1287 m_copydata(q->q_src_m, enccrd->crd_inject,
1288 8, (caddr_t)ctx.pc_iv);
1289 */
1290 crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m,
1291 enccrd->crd_inject, ivsize,
1292 (caddr_t)ctx.pc_iv);
1293 else if (crp->crp_flags & CRYPTO_F_IOV)
1294 /*
1295 cuio_copydata(q->q_src_io,
1296 enccrd->crd_inject, 8,
1297 (caddr_t)ctx.pc_iv);
1298 */
1299 crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io,
1300 enccrd->crd_inject, ivsize,
1301 (caddr_t)ctx.pc_iv);
1302
1303 }
1304
1305 /* Even though key & IV sizes differ from cipher to cipher
1306 * copy / swap the full array lengths. Let the compiler unroll
1307 * the loop to increase the cpu pipeline performance... */
1308 for(i=0; i < 8; i++)
1309 ctx.pc_key[i] = ses->ses_key[i];
1310 for(i=0; i < 4; i++)
1311 SWAP32(ctx.pc_iv[i]);
1312 }
1313
1314 /* Authentication requested */
1315 if (maccrd) {
1316 macoffset = maccrd->crd_skip;
1317
1318 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1319 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1320 else
1321 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1322
1323 for (i = 0; i < 5; i++) {
1324 ctx.pc_hminner[i] = ses->ses_hminner[i];
1325 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1326
1327 HTOLE32(ctx.pc_hminner[i]);
1328 HTOLE32(ctx.pc_hmouter[i]);
1329 }
1330 }
1331
1332 if (enccrd && maccrd) {
1333 /*
1334 * ubsec cannot handle packets where the end of encryption
1335 * and authentication are not the same, or where the
1336 * encrypted part begins before the authenticated part.
1337 */
1338 if (((encoffset + enccrd->crd_len) !=
1339 (macoffset + maccrd->crd_len)) ||
1340 (enccrd->crd_skip < maccrd->crd_skip)) {
1341 err = EINVAL;
1342 goto errout;
1343 }
1344 sskip = maccrd->crd_skip;
1345 cpskip = dskip = enccrd->crd_skip;
1346 stheend = maccrd->crd_len;
1347 dtheend = enccrd->crd_len;
1348 coffset = enccrd->crd_skip - maccrd->crd_skip;
1349 cpoffset = cpskip + dtheend;
1350 #ifdef UBSEC_DEBUG
1351 DPRINTF("mac: skip %d, len %d, inject %d\n",
1352 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1353 DPRINTF("enc: skip %d, len %d, inject %d\n",
1354 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1355 DPRINTF("src: skip %d, len %d\n", sskip, stheend);
1356 DPRINTF("dst: skip %d, len %d\n", dskip, dtheend);
1357 DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1358 coffset, stheend, cpskip, cpoffset);
1359 #endif
1360 } else {
1361 cpskip = dskip = sskip = macoffset + encoffset;
1362 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1363 cpoffset = cpskip + dtheend;
1364 coffset = 0;
1365 }
1366 ctx.pc_offset = htole16(coffset >> 2);
1367
1368 #if 0
1369 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER,
1370 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) {
1371 err = ENOMEM;
1372 goto errout;
1373 }
1374 #endif
1375
1376 if (crp->crp_flags & CRYPTO_F_SKBUF) {
1377 #if 0
1378 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1379 q->q_src_m, BUS_DMA_NOWAIT) != 0) {
1380 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1381 q->q_src_map = NULL;
1382 err = ENOMEM;
1383 goto errout;
1384 }
1385 #endif
1386 err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len);
1387 if (unlikely(err != 0))
1388 goto errout;
1389
1390 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1391 #if 0
1392 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1393 q->q_src_io, BUS_DMA_NOWAIT) != 0) {
1394 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1395 q->q_src_map = NULL;
1396 err = ENOMEM;
1397 goto errout;
1398 }
1399 #endif
1400 err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len);
1401 if (unlikely(err != 0))
1402 goto errout;
1403 }
1404
1405 /*
1406 * Check alignment
1407 */
1408 nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len);
1409
1410 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1411
1412 #ifdef UBSEC_DEBUG
1413 DPRINTF("src skip: %d\n", sskip);
1414 #endif
1415 for (i = j = 0; i < q->q_src_len; i++) {
1416 struct ubsec_pktbuf *pb;
1417 size_t packl = q->q_src_map[i].dma_size;
1418 dma_addr_t packp = q->q_src_map[i].dma_paddr;
1419
1420 if (sskip >= packl) {
1421 sskip -= packl;
1422 continue;
1423 }
1424
1425 packl -= sskip;
1426 packp += sskip;
1427 sskip = 0;
1428
1429 /* maximum fragment size is 0xfffc */
1430 if (packl > 0xfffc) {
1431 DPRINTF("Error: fragment size is bigger than 0xfffc.\n");
1432 err = EIO;
1433 goto errout;
1434 }
1435
1436 if (j == 0)
1437 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1438 else
1439 pb = &dmap->d_dma->d_sbuf[j - 1];
1440
1441 pb->pb_addr = htole32(packp);
1442
1443 if (stheend) {
1444 if (packl > stheend) {
1445 pb->pb_len = htole32(stheend);
1446 stheend = 0;
1447 } else {
1448 pb->pb_len = htole32(packl);
1449 stheend -= packl;
1450 }
1451 } else
1452 pb->pb_len = htole32(packl);
1453
1454 if ((i + 1) == q->q_src_len)
1455 pb->pb_next = 0;
1456 else
1457 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1458 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1459 j++;
1460 }
1461
1462 if (enccrd == NULL && maccrd != NULL) {
1463 /* Authentication only */
1464 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1465 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1466 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next =
1467 htole32(dmap->d_alloc.dma_paddr +
1468 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1469 #ifdef UBSEC_DEBUG
1470 DPRINTF("opkt: %x %x %x\n",
1471 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1472 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1473 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1474 #endif
1475 } else {
1476 if (crp->crp_flags & CRYPTO_F_IOV) {
1477 if (!nicealign) {
1478 err = EINVAL;
1479 goto errout;
1480 }
1481 #if 0
1482 if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1483 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1484 &q->q_dst_map) != 0) {
1485 err = ENOMEM;
1486 goto errout;
1487 }
1488 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1489 q->q_dst_io, BUS_DMA_NOWAIT) != 0) {
1490 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1491 q->q_dst_map = NULL;
1492 goto errout;
1493 }
1494 #endif
1495
1496 /* HW shall copy the result into the source memory */
1497 for(i = 0; i < q->q_src_len; i++)
1498 q->q_dst_map[i] = q->q_src_map[i];
1499
1500 q->q_dst_len = q->q_src_len;
1501 q->q_has_dst = 0;
1502
1503 } else if (crp->crp_flags & CRYPTO_F_SKBUF) {
1504 if (nicealign) {
1505
1506 /* HW shall copy the result into the source memory */
1507 q->q_dst_m = q->q_src_m;
1508 for(i = 0; i < q->q_src_len; i++)
1509 q->q_dst_map[i] = q->q_src_map[i];
1510
1511 q->q_dst_len = q->q_src_len;
1512 q->q_has_dst = 0;
1513
1514 } else {
1515 #ifdef NOTYET
1516 int totlen, len;
1517 struct sk_buff *m, *top, **mp;
1518
1519 totlen = q->q_src_map->dm_mapsize;
1520 if (q->q_src_m->m_flags & M_PKTHDR) {
1521 len = MHLEN;
1522 MGETHDR(m, M_DONTWAIT, MT_DATA);
1523 } else {
1524 len = MLEN;
1525 MGET(m, M_DONTWAIT, MT_DATA);
1526 }
1527 if (m == NULL) {
1528 err = ENOMEM;
1529 goto errout;
1530 }
1531 if (len == MHLEN)
1532 M_DUP_PKTHDR(m, q->q_src_m);
1533 if (totlen >= MINCLSIZE) {
1534 MCLGET(m, M_DONTWAIT);
1535 if (m->m_flags & M_EXT)
1536 len = MCLBYTES;
1537 }
1538 m->m_len = len;
1539 top = NULL;
1540 mp = &top;
1541
1542 while (totlen > 0) {
1543 if (top) {
1544 MGET(m, M_DONTWAIT, MT_DATA);
1545 if (m == NULL) {
1546 m_freem(top);
1547 err = ENOMEM;
1548 goto errout;
1549 }
1550 len = MLEN;
1551 }
1552 if (top && totlen >= MINCLSIZE) {
1553 MCLGET(m, M_DONTWAIT);
1554 if (m->m_flags & M_EXT)
1555 len = MCLBYTES;
1556 }
1557 m->m_len = len = min(totlen, len);
1558 totlen -= len;
1559 *mp = m;
1560 mp = &m->m_next;
1561 }
1562 q->q_dst_m = top;
1563 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1564 cpskip, cpoffset);
1565 if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1566 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1567 &q->q_dst_map) != 0) {
1568 err = ENOMEM;
1569 goto errout;
1570 }
1571 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1572 q->q_dst_map, q->q_dst_m,
1573 BUS_DMA_NOWAIT) != 0) {
1574 bus_dmamap_destroy(sc->sc_dmat,
1575 q->q_dst_map);
1576 q->q_dst_map = NULL;
1577 err = ENOMEM;
1578 goto errout;
1579 }
1580 #else
1581 device_printf(sc->sc_dev,
1582 "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n",
1583 __FILE__, __LINE__);
1584 err = EINVAL;
1585 goto errout;
1586 #endif
1587 }
1588 } else {
1589 err = EINVAL;
1590 goto errout;
1591 }
1592
1593 #ifdef UBSEC_DEBUG
1594 DPRINTF("dst skip: %d\n", dskip);
1595 #endif
1596 for (i = j = 0; i < q->q_dst_len; i++) {
1597 struct ubsec_pktbuf *pb;
1598 size_t packl = q->q_dst_map[i].dma_size;
1599 dma_addr_t packp = q->q_dst_map[i].dma_paddr;
1600
1601 if (dskip >= packl) {
1602 dskip -= packl;
1603 continue;
1604 }
1605
1606 packl -= dskip;
1607 packp += dskip;
1608 dskip = 0;
1609
1610 if (packl > 0xfffc) {
1611 DPRINTF("Error: fragment size is bigger than 0xfffc.\n");
1612 err = EIO;
1613 goto errout;
1614 }
1615
1616 if (j == 0)
1617 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1618 else
1619 pb = &dmap->d_dma->d_dbuf[j - 1];
1620
1621 pb->pb_addr = htole32(packp);
1622
1623 if (dtheend) {
1624 if (packl > dtheend) {
1625 pb->pb_len = htole32(dtheend);
1626 dtheend = 0;
1627 } else {
1628 pb->pb_len = htole32(packl);
1629 dtheend -= packl;
1630 }
1631 } else
1632 pb->pb_len = htole32(packl);
1633
1634 if ((i + 1) == q->q_dst_len) {
1635 if (maccrd)
1636 /* Authentication:
1637 * The last fragment of the output buffer
1638 * contains the HMAC. */
1639 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1640 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1641 else
1642 pb->pb_next = 0;
1643 } else
1644 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1645 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1646 j++;
1647 }
1648 }
1649
1650 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1651 offsetof(struct ubsec_dmachunk, d_ctx));
1652
1653 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1654 /* new Broadcom cards with dynamic long command context structure */
1655
1656 if (enccrd != NULL &&
1657 enccrd->crd_alg == CRYPTO_AES_CBC)
1658 {
1659 struct ubsec_pktctx_aes128 *ctxaes128;
1660 struct ubsec_pktctx_aes192 *ctxaes192;
1661 struct ubsec_pktctx_aes256 *ctxaes256;
1662
1663 switch(ses->ses_keysize)
1664 {
1665 /* AES 128bit */
1666 case 128:
1667 ctxaes128 = (struct ubsec_pktctx_aes128 *)
1668 (dmap->d_alloc.dma_vaddr +
1669 offsetof(struct ubsec_dmachunk, d_ctx));
1670
1671 ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128));
1672 ctxaes128->pc_type = ctx.pc_type;
1673 ctxaes128->pc_flags = ctx.pc_flags;
1674 ctxaes128->pc_offset = ctx.pc_offset;
1675 for (i = 0; i < 4; i++)
1676 ctxaes128->pc_aeskey[i] = ctx.pc_key[i];
1677 for (i = 0; i < 5; i++)
1678 ctxaes128->pc_hminner[i] = ctx.pc_hminner[i];
1679 for (i = 0; i < 5; i++)
1680 ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i];
1681 for (i = 0; i < 4; i++)
1682 ctxaes128->pc_iv[i] = ctx.pc_iv[i];
1683 break;
1684
1685 /* AES 192bit */
1686 case 192:
1687 ctxaes192 = (struct ubsec_pktctx_aes192 *)
1688 (dmap->d_alloc.dma_vaddr +
1689 offsetof(struct ubsec_dmachunk, d_ctx));
1690
1691 ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192));
1692 ctxaes192->pc_type = ctx.pc_type;
1693 ctxaes192->pc_flags = ctx.pc_flags;
1694 ctxaes192->pc_offset = ctx.pc_offset;
1695 for (i = 0; i < 6; i++)
1696 ctxaes192->pc_aeskey[i] = ctx.pc_key[i];
1697 for (i = 0; i < 5; i++)
1698 ctxaes192->pc_hminner[i] = ctx.pc_hminner[i];
1699 for (i = 0; i < 5; i++)
1700 ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i];
1701 for (i = 0; i < 4; i++)
1702 ctxaes192->pc_iv[i] = ctx.pc_iv[i];
1703 break;
1704
1705 /* AES 256bit */
1706 case 256:
1707 ctxaes256 = (struct ubsec_pktctx_aes256 *)
1708 (dmap->d_alloc.dma_vaddr +
1709 offsetof(struct ubsec_dmachunk, d_ctx));
1710
1711 ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256));
1712 ctxaes256->pc_type = ctx.pc_type;
1713 ctxaes256->pc_flags = ctx.pc_flags;
1714 ctxaes256->pc_offset = ctx.pc_offset;
1715 for (i = 0; i < 8; i++)
1716 ctxaes256->pc_aeskey[i] = ctx.pc_key[i];
1717 for (i = 0; i < 5; i++)
1718 ctxaes256->pc_hminner[i] = ctx.pc_hminner[i];
1719 for (i = 0; i < 5; i++)
1720 ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i];
1721 for (i = 0; i < 4; i++)
1722 ctxaes256->pc_iv[i] = ctx.pc_iv[i];
1723 break;
1724
1725 }
1726 } else {
1727 /*
1728 * [3]DES / MD5_HMAC / SHA1_HMAC
1729 *
1730 * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without
1731 * encryption.
1732 */
1733 struct ubsec_pktctx_des *ctxdes;
1734
1735 ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr +
1736 offsetof(struct ubsec_dmachunk, d_ctx));
1737
1738 ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des));
1739 ctxdes->pc_type = ctx.pc_type;
1740 ctxdes->pc_flags = ctx.pc_flags;
1741 ctxdes->pc_offset = ctx.pc_offset;
1742 for (i = 0; i < 6; i++)
1743 ctxdes->pc_deskey[i] = ctx.pc_key[i];
1744 for (i = 0; i < 5; i++)
1745 ctxdes->pc_hminner[i] = ctx.pc_hminner[i];
1746 for (i = 0; i < 5; i++)
1747 ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i];
1748 ctxdes->pc_iv[0] = ctx.pc_iv[0];
1749 ctxdes->pc_iv[1] = ctx.pc_iv[1];
1750 }
1751 } else
1752 {
1753 /* old Broadcom card with fixed small command context structure */
1754
1755 /*
1756 * [3]DES / MD5_HMAC / SHA1_HMAC
1757 */
1758 struct ubsec_pktctx *ctxs;
1759
1760 ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr +
1761 offsetof(struct ubsec_dmachunk, d_ctx));
1762
1763 /* transform generic context into small context */
1764 for (i = 0; i < 6; i++)
1765 ctxs->pc_deskey[i] = ctx.pc_key[i];
1766 for (i = 0; i < 5; i++)
1767 ctxs->pc_hminner[i] = ctx.pc_hminner[i];
1768 for (i = 0; i < 5; i++)
1769 ctxs->pc_hmouter[i] = ctx.pc_hmouter[i];
1770 ctxs->pc_iv[0] = ctx.pc_iv[0];
1771 ctxs->pc_iv[1] = ctx.pc_iv[1];
1772 ctxs->pc_flags = ctx.pc_flags;
1773 ctxs->pc_offset = ctx.pc_offset;
1774 }
1775
1776 #ifdef UBSEC_VERBOSE_DEBUG
1777 DPRINTF("spin_lock_irqsave\n");
1778 #endif
1779 spin_lock_irqsave(&sc->sc_ringmtx, flags);
1780 //spin_lock_irq(&sc->sc_ringmtx);
1781
1782 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1783 sc->sc_nqueue++;
1784 ubsecstats.hst_ipackets++;
1785 ubsecstats.hst_ibytes += stheend;
1786 ubsec_feed(sc);
1787
1788 #ifdef UBSEC_VERBOSE_DEBUG
1789 DPRINTF("spin_unlock_irqrestore\n");
1790 #endif
1791 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1792 //spin_unlock_irq(&sc->sc_ringmtx);
1793
1794 return (0);
1795
1796 errout:
1797 if (q != NULL) {
1798 #ifdef NOTYET
1799 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1800 m_freem(q->q_dst_m);
1801 #endif
1802
1803 if ((q->q_has_dst == 1) && q->q_dst_len > 0) {
1804 #if 0
1805 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1806 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1807 #endif
1808 dma_unmap(sc, q->q_dst_map, q->q_dst_len);
1809 }
1810 if (q->q_src_len > 0) {
1811 #if 0
1812 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1813 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1814 #endif
1815 dma_unmap(sc, q->q_src_map, q->q_src_len);
1816 }
1817
1818 #ifdef UBSEC_VERBOSE_DEBUG
1819 DPRINTF("spin_lock_irqsave\n");
1820 #endif
1821 spin_lock_irqsave(&sc->sc_ringmtx, flags);
1822 //spin_lock_irq(&sc->sc_ringmtx);
1823
1824 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1825
1826 #ifdef UBSEC_VERBOSE_DEBUG
1827 DPRINTF("spin_unlock_irqrestore\n");
1828 #endif
1829 spin_unlock_irqrestore(&sc->sc_ringmtx, flags);
1830 //spin_unlock_irq(&sc->sc_ringmtx);
1831
1832 }
1833 if (err == EINVAL)
1834 ubsecstats.hst_invalid++;
1835 else
1836 ubsecstats.hst_nomem++;
1837 errout2:
1838 crp->crp_etype = err;
1839 crypto_done(crp);
1840
1841 #ifdef UBSEC_DEBUG
1842 DPRINTF("%s() err = %x\n", __FUNCTION__, err);
1843 #endif
1844
1845 return (0);
1846 }
1847
1848 void
1849 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1850 {
1851 struct cryptop *crp = (struct cryptop *)q->q_crp;
1852 struct cryptodesc *crd;
1853 struct ubsec_dma *dmap = q->q_dma;
1854 int ivsize = 8;
1855
1856 #ifdef UBSEC_DEBUG
1857 DPRINTF("%s()\n", __FUNCTION__);
1858 #endif
1859
1860 ubsecstats.hst_opackets++;
1861 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1862
1863 #if 0
1864 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0,
1865 dmap->d_alloc.dma_map->dm_mapsize,
1866 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1867 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1868 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1869 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1870 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1871 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1872 }
1873 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
1874 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1875 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1876 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1877 #endif
1878
1879 if ((q->q_has_dst == 1) && q->q_dst_len > 0)
1880 dma_unmap(sc, q->q_dst_map, q->q_dst_len);
1881
1882 dma_unmap(sc, q->q_src_map, q->q_src_len);
1883
1884 #ifdef NOTYET
1885 if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) {
1886 m_freem(q->q_src_m);
1887 crp->crp_buf = (caddr_t)q->q_dst_m;
1888 }
1889 #endif
1890
1891 /* copy out IV for future use */
1892 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1893 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1894 if (crd->crd_alg != CRYPTO_DES_CBC &&
1895 crd->crd_alg != CRYPTO_3DES_CBC &&
1896 crd->crd_alg != CRYPTO_AES_CBC)
1897 continue;
1898
1899 if (crd->crd_alg == CRYPTO_AES_CBC)
1900 ivsize = 16;
1901 else
1902 ivsize = 8;
1903
1904 if (crp->crp_flags & CRYPTO_F_SKBUF)
1905 #if 0
1906 m_copydata((struct sk_buff *)crp->crp_buf,
1907 crd->crd_skip + crd->crd_len - 8, 8,
1908 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1909 #endif
1910 crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf,
1911 crd->crd_skip + crd->crd_len - ivsize, ivsize,
1912 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1913
1914 else if (crp->crp_flags & CRYPTO_F_IOV) {
1915 #if 0
1916 cuio_copydata((struct uio *)crp->crp_buf,
1917 crd->crd_skip + crd->crd_len - 8, 8,
1918 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1919 #endif
1920 crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf,
1921 crd->crd_skip + crd->crd_len - ivsize, ivsize,
1922 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1923
1924 }
1925 break;
1926 }
1927 }
1928
1929 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1930 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1931 crd->crd_alg != CRYPTO_SHA1_HMAC)
1932 continue;
1933 #if 0
1934 if (crp->crp_flags & CRYPTO_F_SKBUF)
1935 m_copyback((struct sk_buff *)crp->crp_buf,
1936 crd->crd_inject, 12,
1937 dmap->d_dma->d_macbuf);
1938 #endif
1939 #if 0
1940 /* BUG? it does not honor the mac len.. */
1941 crypto_copyback(crp->crp_flags, crp->crp_buf,
1942 crd->crd_inject, 12,
1943 (caddr_t)dmap->d_dma->d_macbuf);
1944 #endif
1945 crypto_copyback(crp->crp_flags, crp->crp_buf,
1946 crd->crd_inject,
1947 sc->sc_sessions[q->q_sesn].ses_mlen,
1948 (caddr_t)dmap->d_dma->d_macbuf);
1949 #if 0
1950 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1951 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1952 crp->crp_mac, 12);
1953 #endif
1954 break;
1955 }
1956 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1957 crypto_done(crp);
1958 }
1959
1960 void
1961 ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset)
1962 {
1963 int i, j, dlen, slen;
1964 caddr_t dptr, sptr;
1965
1966 j = 0;
1967 sptr = srcm->data;
1968 slen = srcm->len;
1969 dptr = dstm->data;
1970 dlen = dstm->len;
1971
1972 while (1) {
1973 for (i = 0; i < min(slen, dlen); i++) {
1974 if (j < hoffset || j >= toffset)
1975 *dptr++ = *sptr++;
1976 slen--;
1977 dlen--;
1978 j++;
1979 }
1980 if (slen == 0) {
1981 srcm = srcm->next;
1982 if (srcm == NULL)
1983 return;
1984 sptr = srcm->data;
1985 slen = srcm->len;
1986 }
1987 if (dlen == 0) {
1988 dstm = dstm->next;
1989 if (dstm == NULL)
1990 return;
1991 dptr = dstm->data;
1992 dlen = dstm->len;
1993 }
1994 }
1995 }
1996
1997 int
1998 ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma,
1999 size_t size, int mapflags)
2000 {
2001 dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv,
2002 size, &dma->dma_paddr, GFP_KERNEL);
2003
2004 if (likely(dma->dma_vaddr))
2005 {
2006 dma->dma_size = size;
2007 return (0);
2008 }
2009
2010 DPRINTF("could not allocate %d bytes of coherent memory.\n", size);
2011
2012 return (1);
2013 }
2014
2015 void
2016 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
2017 {
2018 dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr,
2019 dma->dma_paddr);
2020 }
2021
2022 /*
2023 * Resets the board. Values in the regesters are left as is
2024 * from the reset (i.e. initial values are assigned elsewhere).
2025 */
2026 void
2027 ubsec_reset_board(struct ubsec_softc *sc)
2028 {
2029 volatile u_int32_t ctrl;
2030
2031 #ifdef UBSEC_DEBUG
2032 DPRINTF("%s()\n", __FUNCTION__);
2033 #endif
2034 DPRINTF("Send reset signal to chip.\n");
2035
2036 ctrl = READ_REG(sc, BS_CTRL);
2037 ctrl |= BS_CTRL_RESET;
2038 WRITE_REG(sc, BS_CTRL, ctrl);
2039
2040 /*
2041 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
2042 */
2043 DELAY(10);
2044 }
2045
2046 /*
2047 * Init Broadcom registers
2048 */
2049 void
2050 ubsec_init_board(struct ubsec_softc *sc)
2051 {
2052 u_int32_t ctrl;
2053
2054 #ifdef UBSEC_DEBUG
2055 DPRINTF("%s()\n", __FUNCTION__);
2056 #endif
2057 DPRINTF("Initialize chip.\n");
2058
2059 ctrl = READ_REG(sc, BS_CTRL);
2060 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
2061 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR;
2062
2063 WRITE_REG(sc, BS_CTRL, ctrl);
2064
2065 /* Set chip capabilities (BCM5365P) */
2066 sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES;
2067 }
2068
2069 /*
2070 * Clean up after a chip crash.
2071 * It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2072 */
2073 void
2074 ubsec_cleanchip(struct ubsec_softc *sc)
2075 {
2076 struct ubsec_q *q;
2077
2078 #ifdef UBSEC_DEBUG
2079 DPRINTF("%s()\n", __FUNCTION__);
2080 #endif
2081 DPRINTF("Clean up queues after chip crash.\n");
2082
2083 while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2084 q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip);
2085 BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
2086 ubsec_free_q(sc, q);
2087 }
2088 }
2089
2090 /*
2091 * free a ubsec_q
2092 * It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2093 */
2094 int
2095 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2096 {
2097 struct ubsec_q *q2;
2098 struct cryptop *crp;
2099 int npkts;
2100 int i;
2101
2102 #ifdef UBSEC_DEBUG
2103 DPRINTF("%s()\n", __FUNCTION__);
2104 #endif
2105
2106 npkts = q->q_nstacked_mcrs;
2107
2108 for (i = 0; i < npkts; i++) {
2109 if(q->q_stacked_mcr[i]) {
2110 q2 = q->q_stacked_mcr[i];
2111
2112 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2113 #ifdef NOTYET
2114 m_freem(q2->q_dst_m);
2115 #else
2116 printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__);
2117 #endif
2118
2119 crp = (struct cryptop *)q2->q_crp;
2120
2121 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2122
2123 crp->crp_etype = EFAULT;
2124 crypto_done(crp);
2125 } else {
2126 break;
2127 }
2128 }
2129
2130 /*
2131 * Free header MCR
2132 */
2133 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2134 #ifdef NOTYET
2135 m_freem(q->q_dst_m);
2136 #else
2137 printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__);
2138 #endif
2139
2140 crp = (struct cryptop *)q->q_crp;
2141
2142 BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2143
2144 crp->crp_etype = EFAULT;
2145 crypto_done(crp);
2146 return(0);
2147 }
2148
2149 /*
2150 * Routine to reset the chip and clean up.
2151 * It is assumed that the caller has spin_lock_irq(sc_ringmtx).
2152 */
2153 void
2154 ubsec_totalreset(struct ubsec_softc *sc)
2155 {
2156
2157 #ifdef UBSEC_DEBUG
2158 DPRINTF("%s()\n", __FUNCTION__);
2159 #endif
2160 DPRINTF("initiate total chip reset.. \n");
2161 ubsec_reset_board(sc);
2162 ubsec_init_board(sc);
2163 ubsec_cleanchip(sc);
2164 }
2165
2166 void
2167 ubsec_dump_pb(struct ubsec_pktbuf *pb)
2168 {
2169 printf("addr 0x%x (0x%x) next 0x%x\n",
2170 pb->pb_addr, pb->pb_len, pb->pb_next);
2171 }
2172
2173 void
2174 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2175 {
2176 struct ubsec_mcr_add *ma;
2177 int i;
2178
2179 printf("MCR:\n");
2180 printf(" pkts: %u, flags 0x%x\n",
2181 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2182 ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2183 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2184 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2185 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2186 letoh16(ma->mcr_reserved));
2187 printf(" %d: ipkt ", i);
2188 ubsec_dump_pb(&ma->mcr_ipktbuf);
2189 printf(" %d: opkt ", i);
2190 ubsec_dump_pb(&ma->mcr_opktbuf);
2191 ma++;
2192 }
2193 printf("END MCR\n");
2194 }
2195
2196 static int __init mod_init(void) {
2197 return ssb_driver_register(&ubsec_ssb_driver);
2198 }
2199
2200 static void __exit mod_exit(void) {
2201 ssb_driver_unregister(&ubsec_ssb_driver);
2202 }
2203
2204 module_init(mod_init);
2205 module_exit(mod_exit);
2206
2207 // Meta information
2208 MODULE_AUTHOR("Daniel Mueller <daniel@danm.de>");
2209 MODULE_LICENSE("BSD");
2210 MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core");
2211 MODULE_VERSION(DRV_MODULE_VERSION);
2212
OpenWrt Source Repository