2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 /* FIXME: convert nasty volatile register derefs to readl/writel calls */
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <asm/paccess.h>
30 #include <asm/amazon/irq.h>
31 #include <asm/amazon/amazon.h>
33 #define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr))
34 #ifndef AMAZON_PCI_MEM_BASE
35 #define AMAZON_PCI_MEM_BASE 0xb2000000
37 #define AMAZON_PCI_MEM_SIZE 0x00400000
38 #define AMAZON_PCI_IO_BASE 0xb2400000
39 #define AMAZON_PCI_IO_SIZE 0x00200000
41 #define AMAZON_PCI_CFG_BUSNUM_SHF 16
42 #define AMAZON_PCI_CFG_DEVNUM_SHF 11
43 #define AMAZON_PCI_CFG_FUNNUM_SHF 8
45 #define PCI_ACCESS_READ 0
46 #define PCI_ACCESS_WRITE 1
48 static struct resource pci_io_resource
= {
49 .name
= "io pci IO space",
51 .start
= AMAZON_PCI_IO_BASE
,
52 .end
= AMAZON_PCI_IO_BASE
+ AMAZON_PCI_IO_SIZE
- 1,
55 .end
= 0x00002000 - 1,
57 .flags
= IORESOURCE_IO
60 static struct resource pci_mem_resource
= {
61 .name
= "ext pci memory space",
62 .start
= AMAZON_PCI_MEM_BASE
,
63 .end
= AMAZON_PCI_MEM_BASE
+ AMAZON_PCI_MEM_SIZE
- 1,
64 .flags
= IORESOURCE_MEM
67 static int amazon_pci_config_access(unsigned char access_type
,
68 struct pci_bus
*bus
, unsigned int devfn
, unsigned int where
, u32
*data
)
75 /* Amazon support slot from 0 to 15 */
76 /* devfn 0 & 0x20 is itself */
77 if ((bus
->number
!= 0) || (devfn
> 0x7f) || (devfn
== 0) || (devfn
== 0x20))
80 local_irq_save(flags
);
82 pci_addr
= AMAZON_PCI_CFG_BASE
|
83 bus
->number
<< AMAZON_PCI_CFG_BUSNUM_SHF
|
84 devfn
<< AMAZON_PCI_CFG_FUNNUM_SHF
|
87 if (access_type
== PCI_ACCESS_WRITE
)
89 #ifdef CONFIG_SWAP_IO_SPACE
92 ret
= put_dbe(val
, (u32
*)pci_addr
);
94 ret
= get_dbe(val
, (u32
*)pci_addr
);
95 #ifdef CONFIG_SWAP_IO_SPACE
102 amazon_writel(amazon_readl(PCI_MODE
) & (~(1<<PCI_MODE_cfgok_bit
)), PCI_MODE
);
103 amazon_writel(amazon_readl(STATUS_COMMAND_ADDR
), STATUS_COMMAND_ADDR
);
104 amazon_writel(amazon_readl(PCI_MODE
) | (~(1<<PCI_MODE_cfgok_bit
)), PCI_MODE
);
106 local_irq_restore(flags
);
108 if (((*data
) == 0xffffffff) && (access_type
== PCI_ACCESS_READ
))
115 static int amazon_pci_read(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32
*val
)
119 if (amazon_pci_config_access(PCI_ACCESS_READ
, bus
, devfn
, where
, &data
))
120 return PCIBIOS_DEVICE_NOT_FOUND
;
123 *val
= (data
>> ((where
& 3) << 3)) & 0xff;
125 *val
= (data
>> ((where
& 3) << 3)) & 0xffff;
129 return PCIBIOS_SUCCESSFUL
;
133 static int amazon_pci_write(struct pci_bus
*bus
, unsigned int devfn
, int where
, int size
, u32 val
)
141 if (amazon_pci_config_access(PCI_ACCESS_READ
, bus
, devfn
, where
, &data
))
142 return PCIBIOS_DEVICE_NOT_FOUND
;
145 data
= (data
& ~(0xff << ((where
& 3) << 3))) |
146 (val
<< ((where
& 3) << 3));
148 data
= (data
& ~(0xffff << ((where
& 3) << 3))) |
149 (val
<< ((where
& 3) << 3));
152 if (amazon_pci_config_access(PCI_ACCESS_WRITE
, bus
, devfn
, where
, &data
))
153 return PCIBIOS_DEVICE_NOT_FOUND
;
155 return PCIBIOS_SUCCESSFUL
;
158 static struct pci_ops amazon_pci_ops
= {
163 static struct pci_controller amazon_pci_controller
= {
164 .pci_ops
= &amazon_pci_ops
,
165 .mem_resource
= &pci_mem_resource
,
166 .mem_offset
= 0x00000000UL
,
167 .io_resource
= &pci_io_resource
,
168 .io_offset
= 0x00000000UL
,
171 int __init
pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
175 /* IDSEL = AD29 --> USB Host Controller */
176 return INT_NUM_IM2_IRL15
;
178 /* IDSEL = AD30 --> mini PCI connector */
179 return INT_NUM_IM2_IRL14
;
181 printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot
, pin
);
186 int pcibios_plat_dev_init(struct pci_dev
*dev
)
189 case INT_NUM_IM2_IRL15
:
191 * IDSEL = AD29 --> USB Host Controller
192 * PCI_INTA/B/C--GPIO Port0.2--EXIN3
196 (*AMAZON_GPIO_P0_DIR
) = (*AMAZON_GPIO_P0_DIR
) & 0xfffffffb;
197 (*AMAZON_GPIO_P0_ALTSEL0
) = (*AMAZON_GPIO_P0_ALTSEL0
)| 4;
198 (*AMAZON_GPIO_P0_ALTSEL1
) = (*AMAZON_GPIO_P0_ALTSEL1
)& 0xfffffffb;
199 (*AMAZON_GPIO_P0_PUDSEL
) = (*AMAZON_GPIO_P0_PUDSEL
) | 4;
200 (*AMAZON_GPIO_P0_PUDEN
) = (*AMAZON_GPIO_P0_PUDEN
) | 4;
201 //External Interrupt Node
202 (*AMAZON_ICU_EXTINTCR
) = (*AMAZON_ICU_EXTINTCR
)|0x6000; /* Low Level triggered */
203 (*AMAZON_ICU_IRNEN
) = (*AMAZON_ICU_IRNEN
)|0x8;
204 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, dev
->irq
);
206 case INT_NUM_IM2_IRL14
:
208 * IDSEL = AD30 --> mini PCI connector
209 * PCI_INTA--GPIO Port0.1--EXIN2
213 (*AMAZON_GPIO_P0_DIR
) = (*AMAZON_GPIO_P0_DIR
) & 0xfffffffd;
214 (*AMAZON_GPIO_P0_ALTSEL0
) = (*AMAZON_GPIO_P0_ALTSEL0
)| 2;
215 (*AMAZON_GPIO_P0_ALTSEL1
) = (*AMAZON_GPIO_P0_ALTSEL1
)& 0xfffffffd;
216 (*AMAZON_GPIO_P0_PUDSEL
) = (*AMAZON_GPIO_P0_PUDSEL
) | 2;
217 (*AMAZON_GPIO_P0_PUDEN
) = (*AMAZON_GPIO_P0_PUDEN
) | 2;
218 //External Interrupt Node
219 (*AMAZON_ICU_EXTINTCR
) = (*AMAZON_ICU_EXTINTCR
)|0x600;
220 (*AMAZON_ICU_IRNEN
) = (*AMAZON_ICU_IRNEN
)|0x4;
221 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, dev
->irq
);
229 int __init
amazon_pci_init(void)
233 #ifdef CONFIG_SWAP_IO_SPACE
234 AMAZON_PCI_REG32(IRM
) = AMAZON_PCI_REG32(IRM
) | (1<<27) | (1<<28);
238 AMAZON_PCI_REG32(CLOCK_CONTROL
) = AMAZON_PCI_REG32(CLOCK_CONTROL
) | (1<<ARB_CTRL_bit
);
239 amazon_writel(amazon_readl(PCI_MODE
) & (~(1<<PCI_MODE_cfgok_bit
)), PCI_MODE
);
241 AMAZON_PCI_REG32(STATUS_COMMAND_ADDR
) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR
) | (1<<BUS_MASTER_ENABLE_BIT
) |(1<<MEM_SPACE_ENABLE_BIT
);
243 temp_buffer
= AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR
);
244 temp_buffer
= temp_buffer
| (1<< INTERNAL_ARB_ENABLE_BIT
);
245 temp_buffer
= temp_buffer
& ~(3<< PCI_MASTER0_REQ_MASK_2BITS
);
246 temp_buffer
= temp_buffer
& ~(3<< PCI_MASTER0_GNT_MASK_2BITS
);
249 temp_buffer
= temp_buffer
& ~(3<< PCI_MASTER1_REQ_MASK_2BITS
);
250 temp_buffer
= temp_buffer
& ~(3<< PCI_MASTER1_GNT_MASK_2BITS
);
252 /* external master */
253 temp_buffer
= temp_buffer
& ~(3<< PCI_MASTER2_REQ_MASK_2BITS
);
254 temp_buffer
= temp_buffer
& ~(3<< PCI_MASTER2_GNT_MASK_2BITS
);
256 AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR
) = temp_buffer
;
259 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_0
) = 0xb2000000;
260 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_1
) = 0xb2100000;
261 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_2
) = 0xb2200000;
262 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_3
) = 0xb2300000;
263 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_4
) = 0xb2400000;
264 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5
) = 0xb2500000;
265 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6
) = 0xb2600000;
266 AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7
) = 0xb2700000;
268 AMAZON_PCI_REG32(BAR11_MASK
) = 0x0c000008;
269 AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11
) = 0x0;
270 AMAZON_PCI_REG32(BAR1_ADDR
) = 0x0;
271 amazon_writel(amazon_readl(PCI_MODE
) | (~(1<<PCI_MODE_cfgok_bit
)), PCI_MODE
);
272 //use 8 dw burse length
273 AMAZON_PCI_REG32(FPI_BURST_LENGTH
) = 0x303;
275 amazon_pci_controller
.io_map_base
= (unsigned long)ioremap(AMAZON_PCI_IO_BASE
, AMAZON_PCI_IO_SIZE
- 1);
276 register_pci_controller(&amazon_pci_controller
);
279 arch_initcall(amazon_pci_init
);