4f90eb1b29b446d195dbcc39cc3e83566c11868c
2 * Copyright (C) 2006, 2007 Felix Fietkau, Eugene Konev
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <linux/delay.h>
23 #include <asm/addrspace.h>
26 #define AR7_REGS_BASE 0x08610000
28 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
29 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
30 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
31 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
32 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
33 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
34 #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
35 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
36 #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
37 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
38 #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
39 #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
40 #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
42 #define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
43 #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
44 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
46 #define AR7_RESET_PEREPHERIAL 0x0
47 #define AR7_RESET_SOFTWARE 0x4
48 #define AR7_RESET_STATUS 0x8
50 #define AR7_RESET_BIT_CPMAC_LO 17
51 #define AR7_RESET_BIT_CPMAC_HI 21
52 #define AR7_RESET_BIT_MDIO 22
53 #define AR7_RESET_BIT_EPHY 26
55 /* GPIO control registers */
56 #define AR7_GPIO_INPUT 0x0
57 #define AR7_GPIO_OUTPUT 0x4
58 #define AR7_GPIO_DIR 0x8
59 #define AR7_GPIO_ENABLE 0xc
61 #define AR7_CHIP_7100 0x18
62 #define AR7_CHIP_7200 0x2b
63 #define AR7_CHIP_7300 0x05
66 #define AR7_IRQ_UART0 15
67 #define AR7_IRQ_UART1 16
70 #define AR7_AFE_CLOCK 35328000
71 #define AR7_REF_CLOCK 25000000
72 #define AR7_XTAL_CLOCK 24000000
74 struct plat_cpmac_data
{
81 struct plat_dsl_data
{
86 extern int ar7_cpu_clock
, ar7_bus_clock
, ar7_dsp_clock
;
88 static inline u16
ar7_chip_id(void)
90 return readl((void *)KSEG1ADDR(AR7_REGS_GPIO
+ 0x14)) & 0xffff;
93 static inline u8
ar7_chip_rev(void)
95 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO
+ 0x14)) >> 16) & 0xff;
98 static inline int ar7_cpu_freq(void)
100 return ar7_cpu_clock
;
103 static inline int ar7_bus_freq(void)
105 return ar7_bus_clock
;
108 static inline int ar7_vbus_freq(void)
110 return ar7_bus_clock
/ 2;
112 #define ar7_cpmac_freq ar7_vbus_freq
114 static inline int ar7_dsp_freq(void)
116 return ar7_dsp_clock
;
119 static inline int ar7_has_high_cpmac(void)
121 u16 chip_id
= ar7_chip_id();
130 #define ar7_has_high_vlynq ar7_has_high_cpmac
131 #define ar7_has_second_uart ar7_has_high_cpmac
133 static inline void ar7_device_enable(u32 bit
)
136 (void *)KSEG1ADDR(AR7_REGS_RESET
+ AR7_RESET_PEREPHERIAL
);
137 writel(readl(reset_reg
) | (1 << bit
), reset_reg
);
141 static inline void ar7_device_disable(u32 bit
)
144 (void *)KSEG1ADDR(AR7_REGS_RESET
+ AR7_RESET_PEREPHERIAL
);
145 writel(readl(reset_reg
) & ~(1 << bit
), reset_reg
);
149 static inline void ar7_device_reset(u32 bit
)
151 ar7_device_disable(bit
);
152 ar7_device_enable(bit
);
155 static inline void ar7_device_on(u32 bit
)
157 void *power_reg
= (void *)KSEG1ADDR(AR7_REGS_POWER
);
158 writel(readl(power_reg
) | (1 << bit
), power_reg
);
162 static inline void ar7_device_off(u32 bit
)
164 void *power_reg
= (void *)KSEG1ADDR(AR7_REGS_POWER
);
165 writel(readl(power_reg
) & ~(1 << bit
), power_reg
);
169 #endif /* __AR7_H__ */