1 diff -Nru linux-2.6.19.2/arch/mips/Kconfig linux-ar7/arch/mips/Kconfig
2 --- linux-2.6.19.2/arch/mips/Kconfig 2006-12-12 02:32:53.000000000 +0700
3 +++ linux-ar7/arch/mips/Kconfig 2007-01-29 21:52:21.000000000 +0700
9 + bool "Texas Instruments AR7"
11 + select DMA_NONCOHERENT
14 + select SWAP_IO_SPACE
15 + select SYS_HAS_CPU_MIPS32_R1
16 + select SYS_HAS_EARLY_PRINTK
17 + select SYS_SUPPORTS_32BIT_KERNEL
18 + select SYS_SUPPORTS_LITTLE_ENDIAN
19 + select SYS_SUPPORTS_KGDB
20 + select NEED_MULTIPLE_NODES
24 bool "4G Systems MTX-1 board"
25 select DMA_NONCOHERENT
26 diff -Nru linux-2.6.19.2/arch/mips/Makefile linux-ar7/arch/mips/Makefile
27 --- linux-2.6.19.2/arch/mips/Makefile 2006-12-12 02:32:53.000000000 +0700
28 +++ linux-ar7/arch/mips/Makefile 2007-01-29 21:52:21.000000000 +0700
33 +# Texas Instruments AR7
35 +core-$(CONFIG_AR7) += arch/mips/ar7/
36 +cflags-$(CONFIG_AR7) += -Iinclude/asm-mips/ar7
37 +load-$(CONFIG_AR7) += 0xffffffff94100000
40 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
42 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
43 diff -Nru linux-2.6.19.2/arch/mips/kernel/setup.c linux-ar7/arch/mips/kernel/setup.c
44 --- linux-2.6.19.2orig/arch/mips/kernel/setup.c 2006-12-12 02:32:53.000000000 +0700
45 +++ linux-ar7/arch/mips/kernel/setup.c 2007-03-04 22:32:13.000000000 +0700
47 * Initialize the bootmem allocator. It also setup initrd related data
50 -#ifdef CONFIG_SGI_IP27
51 +#ifdef CONFIG_NEED_MULTIPLE_NODES
53 static void __init bootmem_init(void)
59 -#else /* !CONFIG_SGI_IP27 */
60 +#else /* !CONFIG_NEED_MULTIPLE_NODES */
62 static void __init bootmem_init(void)
68 -#endif /* CONFIG_SGI_IP27 */
69 +#endif /* CONFIG_NEED_MULTIPLE_NODES */
72 * arch_mem_init - initialize memory managment subsystem
73 diff -Nru linux-2.6.19.2/arch/mips/kernel/traps.c linux-ar7/arch/mips/kernel/traps.c
74 --- linux-2.6.19.2/arch/mips/kernel/traps.c 2007-01-11 02:10:37.000000000 +0700
75 +++ linux-ar7/arch/mips/kernel/traps.c 2007-03-15 13:19:19.000000000 +0700
76 @@ -1072,11 +1072,6 @@
77 unsigned long exception_handlers[32];
78 unsigned long vi_handlers[64];
81 - * As a side effect of the way this is implemented we're limited
82 - * to interrupt handlers in the address range from
83 - * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
85 void *set_except_vector(int n, void *addr)
87 unsigned long handler = (unsigned long) addr;
88 @@ -1084,9 +1079,15 @@
90 exception_handlers[n] = handler;
91 if (n == 0 && cpu_has_divec) {
92 - *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
93 - (0x03ffffff & (handler >> 2));
94 - flush_icache_range(ebase + 0x200, ebase + 0x204);
95 + /* lui k0, 0x0000 */
96 + *(volatile u32 *)(CAC_BASE+0x200) = 0x3c1a0000 | (handler >> 16);
97 + /* ori k0, 0x0000 */
98 + *(volatile u32 *)(CAC_BASE+0x204) = 0x375a0000 | (handler & 0xffff);
100 + *(volatile u32 *)(CAC_BASE+0x208) = 0x03400008;
102 + *(volatile u32 *)(CAC_BASE+0x20C) = 0x00000000;
103 + flush_icache_range(CAC_BASE+0x200, CAC_BASE+0x210);
105 return (void *)old_handler;