2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
24 static void ar71xx_gpio_irq_dispatch(void)
28 pending
= ar71xx_gpio_rr(GPIO_REG_INT_PENDING
)
29 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
32 do_IRQ(AR71XX_GPIO_IRQ_BASE
+ fls(pending
) - 1);
37 static void ar71xx_gpio_irq_unmask(unsigned int irq
)
39 irq
-= AR71XX_GPIO_IRQ_BASE
;
40 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
41 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) | (1 << irq
));
44 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
47 static void ar71xx_gpio_irq_mask(unsigned int irq
)
49 irq
-= AR71XX_GPIO_IRQ_BASE
;
50 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
51 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) & ~(1 << irq
));
54 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
58 static int ar71xx_gpio_irq_set_type(unsigned int irq
, unsigned int flow_type
)
64 #define ar71xx_gpio_irq_set_type NULL
67 static struct irq_chip ar71xx_gpio_irq_chip
= {
68 .name
= "AR71XX GPIO",
69 .unmask
= ar71xx_gpio_irq_unmask
,
70 .mask
= ar71xx_gpio_irq_mask
,
71 .mask_ack
= ar71xx_gpio_irq_mask
,
72 .set_type
= ar71xx_gpio_irq_set_type
,
75 static struct irqaction ar71xx_gpio_irqaction
= {
77 .name
= "cascade [AR71XX GPIO]",
80 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
81 #define GPIO_INT_ALL 0xffff
83 static void __init
ar71xx_gpio_irq_init(void)
87 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
, 0);
88 ar71xx_gpio_wr(GPIO_REG_INT_PENDING
, 0);
90 /* setup type of all GPIO interrupts to level sensitive */
91 ar71xx_gpio_wr(GPIO_REG_INT_TYPE
, GPIO_INT_ALL
);
93 /* setup polarity of all GPIO interrupts to active high */
94 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY
, GPIO_INT_ALL
);
96 for (i
= AR71XX_GPIO_IRQ_BASE
;
97 i
< AR71XX_GPIO_IRQ_BASE
+ AR71XX_GPIO_IRQ_COUNT
; i
++) {
98 irq_desc
[i
].status
= GPIO_IRQ_INIT_STATUS
;
99 set_irq_chip_and_handler(i
, &ar71xx_gpio_irq_chip
,
103 setup_irq(AR71XX_MISC_IRQ_GPIO
, &ar71xx_gpio_irqaction
);
106 static void ar71xx_misc_irq_dispatch(void)
110 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
)
111 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
113 if (pending
& MISC_INT_UART
)
114 do_IRQ(AR71XX_MISC_IRQ_UART
);
116 else if (pending
& MISC_INT_DMA
)
117 do_IRQ(AR71XX_MISC_IRQ_DMA
);
119 else if (pending
& MISC_INT_PERFC
)
120 do_IRQ(AR71XX_MISC_IRQ_PERFC
);
122 else if (pending
& MISC_INT_TIMER
)
123 do_IRQ(AR71XX_MISC_IRQ_TIMER
);
125 else if (pending
& MISC_INT_OHCI
)
126 do_IRQ(AR71XX_MISC_IRQ_OHCI
);
128 else if (pending
& MISC_INT_ERROR
)
129 do_IRQ(AR71XX_MISC_IRQ_ERROR
);
131 else if (pending
& MISC_INT_GPIO
)
132 ar71xx_gpio_irq_dispatch();
134 else if (pending
& MISC_INT_WDOG
)
135 do_IRQ(AR71XX_MISC_IRQ_WDOG
);
138 spurious_interrupt();
141 static void ar71xx_misc_irq_unmask(unsigned int irq
)
143 irq
-= AR71XX_MISC_IRQ_BASE
;
144 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
145 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) | (1 << irq
));
148 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
151 static void ar71xx_misc_irq_mask(unsigned int irq
)
153 irq
-= AR71XX_MISC_IRQ_BASE
;
154 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
155 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) & ~(1 << irq
));
158 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
161 static void ar724x_misc_irq_ack(unsigned int irq
)
163 irq
-= AR71XX_MISC_IRQ_BASE
;
164 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
,
165 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
) & ~(1 << irq
));
168 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
);
171 static struct irq_chip ar71xx_misc_irq_chip
= {
172 .name
= "AR71XX MISC",
173 .unmask
= ar71xx_misc_irq_unmask
,
174 .mask
= ar71xx_misc_irq_mask
,
177 static struct irqaction ar71xx_misc_irqaction
= {
178 .handler
= no_action
,
179 .name
= "cascade [AR71XX MISC]",
182 static void __init
ar71xx_misc_irq_init(void)
186 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
, 0);
187 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
, 0);
189 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
190 ar71xx_misc_irq_chip
.ack
= ar724x_misc_irq_ack
;
192 ar71xx_misc_irq_chip
.mask_ack
= ar71xx_misc_irq_mask
;
194 for (i
= AR71XX_MISC_IRQ_BASE
;
195 i
< AR71XX_MISC_IRQ_BASE
+ AR71XX_MISC_IRQ_COUNT
; i
++) {
196 irq_desc
[i
].status
= IRQ_DISABLED
;
197 set_irq_chip_and_handler(i
, &ar71xx_misc_irq_chip
,
201 setup_irq(AR71XX_CPU_IRQ_MISC
, &ar71xx_misc_irqaction
);
204 asmlinkage
void plat_irq_dispatch(void)
206 unsigned long pending
;
208 pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
210 if (pending
& STATUSF_IP7
)
211 do_IRQ(AR71XX_CPU_IRQ_TIMER
);
213 else if (pending
& STATUSF_IP2
)
214 do_IRQ(AR71XX_CPU_IRQ_IP2
);
216 else if (pending
& STATUSF_IP4
)
217 do_IRQ(AR71XX_CPU_IRQ_GE0
);
219 else if (pending
& STATUSF_IP5
)
220 do_IRQ(AR71XX_CPU_IRQ_GE1
);
222 else if (pending
& STATUSF_IP3
)
223 do_IRQ(AR71XX_CPU_IRQ_USB
);
225 else if (pending
& STATUSF_IP6
)
226 ar71xx_misc_irq_dispatch();
229 spurious_interrupt();
232 void __init
arch_init_irq(void)
236 ar71xx_misc_irq_init();
238 cp0_perfcount_irq
= AR71XX_MISC_IRQ_PERFC
;
240 ar71xx_gpio_irq_init();