target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irq.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23
  24 static void ar71xx_gpio_irq_dispatch(void)
  25 {
  26         u32 pending;
  27
  28         pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
  29                 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
  30
  31         if (pending)
  32                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
  33         else
  34                 spurious_interrupt();
  35 }
  36
  37 static void ar71xx_gpio_irq_unmask(unsigned int irq)
  38 {
  39         irq -= AR71XX_GPIO_IRQ_BASE;
  40         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
  41                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
  42
  43         /* flush write */
  44         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
  45 }
  46
  47 static void ar71xx_gpio_irq_mask(unsigned int irq)
  48 {
  49         irq -= AR71XX_GPIO_IRQ_BASE;
  50         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
  51                         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
  52
  53         /* flush write */
  54         ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
  55 }
  56
  57 #if 0
  58 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
  59 {
  60         /* TODO: implement */
  61         return 0;
  62 }
  63 #else
  64 #define ar71xx_gpio_irq_set_type        NULL
  65 #endif
  66
  67 static struct irq_chip ar71xx_gpio_irq_chip = {
  68         .name           = "AR71XX GPIO",
  69         .unmask         = ar71xx_gpio_irq_unmask,
  70         .mask           = ar71xx_gpio_irq_mask,
  71         .mask_ack       = ar71xx_gpio_irq_mask,
  72         .set_type       = ar71xx_gpio_irq_set_type,
  73 };
  74
  75 static struct irqaction ar71xx_gpio_irqaction = {
  76         .handler        = no_action,
  77         .name           = "cascade [AR71XX GPIO]",
  78 };
  79
  80 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
  81 #define GPIO_INT_ALL    0xffff
  82
  83 static void __init ar71xx_gpio_irq_init(void)
  84 {
  85         int i;
  86
  87         ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
  88         ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
  89
  90         /* setup type of all GPIO interrupts to level sensitive */
  91         ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
  92
  93         /* setup polarity of all GPIO interrupts to active high */
  94         ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
  95
  96         for (i = AR71XX_GPIO_IRQ_BASE;
  97              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
  98                 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
  99                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 100                                          handle_level_irq);
 101         }
 102
 103         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 104 }
 105
 106 static void ar71xx_misc_irq_dispatch(void)
 107 {
 108         u32 pending;
 109
 110         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 111             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 112
 113         if (pending & MISC_INT_UART)
 114                 do_IRQ(AR71XX_MISC_IRQ_UART);
 115
 116         else if (pending & MISC_INT_DMA)
 117                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 118
 119         else if (pending & MISC_INT_PERFC)
 120                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 121
 122         else if (pending & MISC_INT_TIMER)
 123                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 124
 125         else if (pending & MISC_INT_OHCI)
 126                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 127
 128         else if (pending & MISC_INT_ERROR)
 129                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 130
 131         else if (pending & MISC_INT_GPIO)
 132                 ar71xx_gpio_irq_dispatch();
 133
 134         else if (pending & MISC_INT_WDOG)
 135                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 136
 137         else
 138                 spurious_interrupt();
 139 }
 140
 141 static void ar71xx_misc_irq_unmask(unsigned int irq)
 142 {
 143         irq -= AR71XX_MISC_IRQ_BASE;
 144         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 145                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
 146
 147         /* flush write */
 148         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 149 }
 150
 151 static void ar71xx_misc_irq_mask(unsigned int irq)
 152 {
 153         irq -= AR71XX_MISC_IRQ_BASE;
 154         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
 155                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
 156
 157         /* flush write */
 158         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 159 }
 160
 161 static void ar724x_misc_irq_ack(unsigned int irq)
 162 {
 163         irq -= AR71XX_MISC_IRQ_BASE;
 164         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
 165                 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
 166
 167         /* flush write */
 168         ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
 169 }
 170
 171 static struct irq_chip ar71xx_misc_irq_chip = {
 172         .name           = "AR71XX MISC",
 173         .unmask         = ar71xx_misc_irq_unmask,
 174         .mask           = ar71xx_misc_irq_mask,
 175 };
 176
 177 static struct irqaction ar71xx_misc_irqaction = {
 178         .handler        = no_action,
 179         .name           = "cascade [AR71XX MISC]",
 180 };
 181
 182 static void __init ar71xx_misc_irq_init(void)
 183 {
 184         int i;
 185
 186         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
 187         ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
 188
 189         if (ar71xx_soc == AR71XX_SOC_AR7240)
 190                 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
 191         else
 192                 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
 193
 194         for (i = AR71XX_MISC_IRQ_BASE;
 195              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
 196                 irq_desc[i].status = IRQ_DISABLED;
 197                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 198                                          handle_level_irq);
 199         }
 200
 201         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 202 }
 203
 204 asmlinkage void plat_irq_dispatch(void)
 205 {
 206         unsigned long pending;
 207
 208         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 209
 210         if (pending & STATUSF_IP7)
 211                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 212
 213         else if (pending & STATUSF_IP2)
 214                 do_IRQ(AR71XX_CPU_IRQ_IP2);
 215
 216         else if (pending & STATUSF_IP4)
 217                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 218
 219         else if (pending & STATUSF_IP5)
 220                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 221
 222         else if (pending & STATUSF_IP3)
 223                 do_IRQ(AR71XX_CPU_IRQ_USB);
 224
 225         else if (pending & STATUSF_IP6)
 226                 ar71xx_misc_irq_dispatch();
 227
 228         else
 229                 spurious_interrupt();
 230 }
 231
 232 void __init arch_init_irq(void)
 233 {
 234         mips_cpu_irq_init();
 235
 236         ar71xx_misc_irq_init();
 237
 238         cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
 239
 240         ar71xx_gpio_irq_init();
 241 }