2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
34 static struct resource ath79_mdio0_resources
[] = {
37 .flags
= IORESOURCE_MEM
,
38 .start
= AR71XX_GE0_BASE
,
39 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data
;
45 struct platform_device ath79_mdio0_device
= {
46 .name
= "ag71xx-mdio",
48 .resource
= ath79_mdio0_resources
,
49 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
51 .platform_data
= &ath79_mdio0_data
,
55 static struct resource ath79_mdio1_resources
[] = {
58 .flags
= IORESOURCE_MEM
,
59 .start
= AR71XX_GE1_BASE
,
60 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data
;
66 struct platform_device ath79_mdio1_device
= {
67 .name
= "ag71xx-mdio",
69 .resource
= ath79_mdio1_resources
,
70 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
72 .platform_data
= &ath79_mdio1_data
,
76 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
81 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
83 t
= __raw_readl(base
+ cfg_reg
);
86 __raw_writel(t
, base
+ cfg_reg
);
89 __raw_writel(pll_val
, base
+ pll_reg
);
92 __raw_writel(t
, base
+ cfg_reg
);
96 __raw_writel(t
, base
+ cfg_reg
);
99 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
105 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
111 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
113 t
= __raw_readl(base
+ reg
);
114 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
115 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
116 __raw_writel(t
, base
+ reg
);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
124 unsigned int mii_speed
;
129 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
132 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
135 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
141 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
143 t
= __raw_readl(base
+ reg
);
144 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
145 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
146 __raw_writel(t
, base
+ reg
);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base
= ioremap(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
160 t
= __raw_readl(base
+ AR934X_PLL_SWITCH_CLOCK_CONTROL_REG
);
161 if (t
& AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL
) {
162 ret
= 100 * 1000 * 1000;
166 clk
= clk_get(NULL
, "ref");
168 ret
= clk_get_rate(clk
);
176 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
178 struct platform_device
*mdio_dev
;
179 struct ag71xx_mdio_platform_data
*mdio_data
;
182 if (ath79_soc
== ATH79_SOC_AR9341
||
183 ath79_soc
== ATH79_SOC_AR9342
||
184 ath79_soc
== ATH79_SOC_AR9344
||
185 ath79_soc
== ATH79_SOC_QCA9556
||
186 ath79_soc
== ATH79_SOC_QCA9558
)
192 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
197 case ATH79_SOC_AR7241
:
198 case ATH79_SOC_AR9330
:
199 case ATH79_SOC_AR9331
:
200 case ATH79_SOC_QCA9533
:
201 mdio_dev
= &ath79_mdio1_device
;
202 mdio_data
= &ath79_mdio1_data
;
205 case ATH79_SOC_AR9341
:
206 case ATH79_SOC_AR9342
:
207 case ATH79_SOC_AR9344
:
208 case ATH79_SOC_QCA9556
:
209 case ATH79_SOC_QCA9558
:
211 mdio_dev
= &ath79_mdio0_device
;
212 mdio_data
= &ath79_mdio0_data
;
214 mdio_dev
= &ath79_mdio1_device
;
215 mdio_data
= &ath79_mdio1_data
;
219 case ATH79_SOC_AR7242
:
220 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
221 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
222 AR71XX_ETH0_PLL_SHIFT
);
225 mdio_dev
= &ath79_mdio0_device
;
226 mdio_data
= &ath79_mdio0_data
;
230 mdio_data
->phy_mask
= phy_mask
;
233 case ATH79_SOC_AR7240
:
234 mdio_data
->is_ar7240
= 1;
236 case ATH79_SOC_AR7241
:
237 mdio_data
->builtin_switch
= 1;
240 case ATH79_SOC_AR9330
:
241 mdio_data
->is_ar9330
= 1;
243 case ATH79_SOC_AR9331
:
244 mdio_data
->builtin_switch
= 1;
247 case ATH79_SOC_AR9341
:
248 case ATH79_SOC_AR9342
:
249 case ATH79_SOC_AR9344
:
251 mdio_data
->builtin_switch
= 1;
252 mdio_data
->ref_clock
= ar934x_get_mdio_ref_clock();
253 mdio_data
->mdio_clock
= 6250000;
255 mdio_data
->is_ar934x
= 1;
258 case ATH79_SOC_QCA9533
:
259 mdio_data
->builtin_switch
= 1;
262 case ATH79_SOC_QCA9556
:
263 case ATH79_SOC_QCA9558
:
264 mdio_data
->is_ar934x
= 1;
271 platform_device_register(mdio_dev
);
274 struct ath79_eth_pll_data ath79_eth0_pll_data
;
275 struct ath79_eth_pll_data ath79_eth1_pll_data
;
277 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
279 struct ath79_eth_pll_data
*pll_data
;
284 pll_data
= &ath79_eth0_pll_data
;
287 pll_data
= &ath79_eth1_pll_data
;
295 pll_val
= pll_data
->pll_10
;
298 pll_val
= pll_data
->pll_100
;
301 pll_val
= pll_data
->pll_1000
;
310 static void ath79_set_speed_ge0(int speed
)
312 u32 val
= ath79_get_eth_pll(0, speed
);
314 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
315 val
, AR71XX_ETH0_PLL_SHIFT
);
316 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
319 static void ath79_set_speed_ge1(int speed
)
321 u32 val
= ath79_get_eth_pll(1, speed
);
323 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
324 val
, AR71XX_ETH1_PLL_SHIFT
);
325 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
328 static void ar7242_set_speed_ge0(int speed
)
330 u32 val
= ath79_get_eth_pll(0, speed
);
333 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
334 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
338 static void ar91xx_set_speed_ge0(int speed
)
340 u32 val
= ath79_get_eth_pll(0, speed
);
342 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
343 val
, AR913X_ETH0_PLL_SHIFT
);
344 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
347 static void ar91xx_set_speed_ge1(int speed
)
349 u32 val
= ath79_get_eth_pll(1, speed
);
351 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
352 val
, AR913X_ETH1_PLL_SHIFT
);
353 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
356 static void ar934x_set_speed_ge0(int speed
)
359 u32 val
= ath79_get_eth_pll(0, speed
);
361 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
362 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
366 static void qca955x_set_speed_xmii(int speed
)
369 u32 val
= ath79_get_eth_pll(0, speed
);
371 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
372 __raw_writel(val
, base
+ QCA955X_PLL_ETH_XMII_CONTROL_REG
);
376 static void qca955x_set_speed_sgmii(int speed
)
379 u32 val
= ath79_get_eth_pll(1, speed
);
381 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
382 __raw_writel(val
, base
+ QCA955X_PLL_ETH_SGMII_CONTROL_REG
);
386 static void ath79_set_speed_dummy(int speed
)
390 static void ath79_ddr_no_flush(void)
394 static void ath79_ddr_flush_ge0(void)
396 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0
);
399 static void ath79_ddr_flush_ge1(void)
401 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1
);
404 static void ar724x_ddr_flush_ge0(void)
406 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0
);
409 static void ar724x_ddr_flush_ge1(void)
411 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1
);
414 static void ar91xx_ddr_flush_ge0(void)
416 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0
);
419 static void ar91xx_ddr_flush_ge1(void)
421 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1
);
424 static void ar933x_ddr_flush_ge0(void)
426 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0
);
429 static void ar933x_ddr_flush_ge1(void)
431 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1
);
434 static struct resource ath79_eth0_resources
[] = {
437 .flags
= IORESOURCE_MEM
,
438 .start
= AR71XX_GE0_BASE
,
439 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
442 .flags
= IORESOURCE_IRQ
,
443 .start
= ATH79_CPU_IRQ(4),
444 .end
= ATH79_CPU_IRQ(4),
448 struct ag71xx_platform_data ath79_eth0_data
= {
449 .reset_bit
= AR71XX_RESET_GE0_MAC
,
452 struct platform_device ath79_eth0_device
= {
455 .resource
= ath79_eth0_resources
,
456 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
458 .platform_data
= &ath79_eth0_data
,
462 static struct resource ath79_eth1_resources
[] = {
465 .flags
= IORESOURCE_MEM
,
466 .start
= AR71XX_GE1_BASE
,
467 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
470 .flags
= IORESOURCE_IRQ
,
471 .start
= ATH79_CPU_IRQ(5),
472 .end
= ATH79_CPU_IRQ(5),
476 struct ag71xx_platform_data ath79_eth1_data
= {
477 .reset_bit
= AR71XX_RESET_GE1_MAC
,
480 struct platform_device ath79_eth1_device
= {
483 .resource
= ath79_eth1_resources
,
484 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
486 .platform_data
= &ath79_eth1_data
,
490 struct ag71xx_switch_platform_data ath79_switch_data
;
492 #define AR71XX_PLL_VAL_1000 0x00110000
493 #define AR71XX_PLL_VAL_100 0x00001099
494 #define AR71XX_PLL_VAL_10 0x00991099
496 #define AR724X_PLL_VAL_1000 0x00110000
497 #define AR724X_PLL_VAL_100 0x00001099
498 #define AR724X_PLL_VAL_10 0x00991099
500 #define AR7242_PLL_VAL_1000 0x16000000
501 #define AR7242_PLL_VAL_100 0x00000101
502 #define AR7242_PLL_VAL_10 0x00001616
504 #define AR913X_PLL_VAL_1000 0x1a000000
505 #define AR913X_PLL_VAL_100 0x13000a44
506 #define AR913X_PLL_VAL_10 0x00441099
508 #define AR933X_PLL_VAL_1000 0x00110000
509 #define AR933X_PLL_VAL_100 0x00001099
510 #define AR933X_PLL_VAL_10 0x00991099
512 #define AR934X_PLL_VAL_1000 0x16000000
513 #define AR934X_PLL_VAL_100 0x00000101
514 #define AR934X_PLL_VAL_10 0x00001616
516 static void __init
ath79_init_eth_pll_data(unsigned int id
)
518 struct ath79_eth_pll_data
*pll_data
;
519 u32 pll_10
, pll_100
, pll_1000
;
523 pll_data
= &ath79_eth0_pll_data
;
526 pll_data
= &ath79_eth1_pll_data
;
533 case ATH79_SOC_AR7130
:
534 case ATH79_SOC_AR7141
:
535 case ATH79_SOC_AR7161
:
536 pll_10
= AR71XX_PLL_VAL_10
;
537 pll_100
= AR71XX_PLL_VAL_100
;
538 pll_1000
= AR71XX_PLL_VAL_1000
;
541 case ATH79_SOC_AR7240
:
542 case ATH79_SOC_AR7241
:
543 pll_10
= AR724X_PLL_VAL_10
;
544 pll_100
= AR724X_PLL_VAL_100
;
545 pll_1000
= AR724X_PLL_VAL_1000
;
548 case ATH79_SOC_AR7242
:
549 pll_10
= AR7242_PLL_VAL_10
;
550 pll_100
= AR7242_PLL_VAL_100
;
551 pll_1000
= AR7242_PLL_VAL_1000
;
554 case ATH79_SOC_AR9130
:
555 case ATH79_SOC_AR9132
:
556 pll_10
= AR913X_PLL_VAL_10
;
557 pll_100
= AR913X_PLL_VAL_100
;
558 pll_1000
= AR913X_PLL_VAL_1000
;
561 case ATH79_SOC_AR9330
:
562 case ATH79_SOC_AR9331
:
563 pll_10
= AR933X_PLL_VAL_10
;
564 pll_100
= AR933X_PLL_VAL_100
;
565 pll_1000
= AR933X_PLL_VAL_1000
;
568 case ATH79_SOC_AR9341
:
569 case ATH79_SOC_AR9342
:
570 case ATH79_SOC_AR9344
:
571 case ATH79_SOC_QCA9533
:
572 case ATH79_SOC_QCA9556
:
573 case ATH79_SOC_QCA9558
:
574 pll_10
= AR934X_PLL_VAL_10
;
575 pll_100
= AR934X_PLL_VAL_100
;
576 pll_1000
= AR934X_PLL_VAL_1000
;
583 if (!pll_data
->pll_10
)
584 pll_data
->pll_10
= pll_10
;
586 if (!pll_data
->pll_100
)
587 pll_data
->pll_100
= pll_100
;
589 if (!pll_data
->pll_1000
)
590 pll_data
->pll_1000
= pll_1000
;
593 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
594 struct ag71xx_platform_data
*pdata
)
601 case ATH79_SOC_AR7130
:
602 case ATH79_SOC_AR7141
:
603 case ATH79_SOC_AR7161
:
604 case ATH79_SOC_AR9130
:
605 case ATH79_SOC_AR9132
:
606 switch (pdata
->phy_if_mode
) {
607 case PHY_INTERFACE_MODE_MII
:
608 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
610 case PHY_INTERFACE_MODE_GMII
:
611 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
613 case PHY_INTERFACE_MODE_RGMII
:
614 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
616 case PHY_INTERFACE_MODE_RMII
:
617 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
622 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
625 case ATH79_SOC_AR7240
:
626 case ATH79_SOC_AR7241
:
627 case ATH79_SOC_AR9330
:
628 case ATH79_SOC_AR9331
:
629 case ATH79_SOC_QCA9533
:
630 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
633 case ATH79_SOC_AR7242
:
636 case ATH79_SOC_AR9341
:
637 case ATH79_SOC_AR9342
:
638 case ATH79_SOC_AR9344
:
639 switch (pdata
->phy_if_mode
) {
640 case PHY_INTERFACE_MODE_MII
:
641 case PHY_INTERFACE_MODE_GMII
:
642 case PHY_INTERFACE_MODE_RGMII
:
643 case PHY_INTERFACE_MODE_RMII
:
650 case ATH79_SOC_QCA9556
:
651 case ATH79_SOC_QCA9558
:
652 switch (pdata
->phy_if_mode
) {
653 case PHY_INTERFACE_MODE_MII
:
654 case PHY_INTERFACE_MODE_RGMII
:
655 case PHY_INTERFACE_MODE_SGMII
:
668 case ATH79_SOC_AR7130
:
669 case ATH79_SOC_AR7141
:
670 case ATH79_SOC_AR7161
:
671 case ATH79_SOC_AR9130
:
672 case ATH79_SOC_AR9132
:
673 switch (pdata
->phy_if_mode
) {
674 case PHY_INTERFACE_MODE_RMII
:
675 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
677 case PHY_INTERFACE_MODE_RGMII
:
678 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
683 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
686 case ATH79_SOC_AR7240
:
687 case ATH79_SOC_AR7241
:
688 case ATH79_SOC_AR9330
:
689 case ATH79_SOC_AR9331
:
690 case ATH79_SOC_QCA9533
:
691 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
694 case ATH79_SOC_AR7242
:
697 case ATH79_SOC_AR9341
:
698 case ATH79_SOC_AR9342
:
699 case ATH79_SOC_AR9344
:
700 switch (pdata
->phy_if_mode
) {
701 case PHY_INTERFACE_MODE_MII
:
702 case PHY_INTERFACE_MODE_GMII
:
709 case ATH79_SOC_QCA9556
:
710 case ATH79_SOC_QCA9558
:
711 switch (pdata
->phy_if_mode
) {
712 case PHY_INTERFACE_MODE_MII
:
713 case PHY_INTERFACE_MODE_RGMII
:
714 case PHY_INTERFACE_MODE_SGMII
:
730 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
735 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
737 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
738 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
740 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
742 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
743 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
748 void __init
ath79_setup_ar934x_eth_cfg(u32 mask
)
753 base
= ioremap(AR934X_GMAC_BASE
, AR934X_GMAC_SIZE
);
755 t
= __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
757 t
&= ~(AR934X_ETH_CFG_RGMII_GMAC0
|
758 AR934X_ETH_CFG_MII_GMAC0
|
759 AR934X_ETH_CFG_GMII_GMAC0
|
760 AR934X_ETH_CFG_SW_ONLY_MODE
|
761 AR934X_ETH_CFG_SW_PHY_SWAP
);
765 __raw_writel(t
, base
+ AR934X_GMAC_REG_ETH_CFG
);
767 __raw_readl(base
+ AR934X_GMAC_REG_ETH_CFG
);
772 void __init
ath79_setup_qca955x_eth_cfg(u32 mask
)
777 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
779 t
= __raw_readl(base
+ QCA955X_GMAC_REG_ETH_CFG
);
781 t
&= ~(QCA955X_ETH_CFG_RGMII_EN
| QCA955X_ETH_CFG_GE0_SGMII
);
785 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
790 static int ath79_eth_instance __initdata
;
791 void __init
ath79_register_eth(unsigned int id
)
793 struct platform_device
*pdev
;
794 struct ag71xx_platform_data
*pdata
;
798 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
802 ath79_init_eth_pll_data(id
);
805 pdev
= &ath79_eth0_device
;
807 pdev
= &ath79_eth1_device
;
809 pdata
= pdev
->dev
.platform_data
;
811 pdata
->max_frame_len
= 1540;
812 pdata
->desc_pktlen_mask
= 0xfff;
814 err
= ath79_setup_phy_if_mode(id
, pdata
);
817 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
822 case ATH79_SOC_AR7130
:
824 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
825 pdata
->set_speed
= ath79_set_speed_ge0
;
827 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
828 pdata
->set_speed
= ath79_set_speed_ge1
;
832 case ATH79_SOC_AR7141
:
833 case ATH79_SOC_AR7161
:
835 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
836 pdata
->set_speed
= ath79_set_speed_ge0
;
838 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
839 pdata
->set_speed
= ath79_set_speed_ge1
;
844 case ATH79_SOC_AR7242
:
846 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
847 AR71XX_RESET_GE0_PHY
;
848 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
849 pdata
->set_speed
= ar7242_set_speed_ge0
;
851 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
852 AR71XX_RESET_GE1_PHY
;
853 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
854 pdata
->set_speed
= ath79_set_speed_dummy
;
857 pdata
->is_ar724x
= 1;
859 if (!pdata
->fifo_cfg1
)
860 pdata
->fifo_cfg1
= 0x0010ffff;
861 if (!pdata
->fifo_cfg2
)
862 pdata
->fifo_cfg2
= 0x015500aa;
863 if (!pdata
->fifo_cfg3
)
864 pdata
->fifo_cfg3
= 0x01f00140;
867 case ATH79_SOC_AR7241
:
869 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
871 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
873 case ATH79_SOC_AR7240
:
875 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
876 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
877 pdata
->set_speed
= ath79_set_speed_dummy
;
879 pdata
->phy_mask
= BIT(4);
881 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
882 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
883 pdata
->set_speed
= ath79_set_speed_dummy
;
885 pdata
->speed
= SPEED_1000
;
886 pdata
->duplex
= DUPLEX_FULL
;
887 pdata
->switch_data
= &ath79_switch_data
;
889 ath79_switch_data
.phy_poll_mask
|= BIT(4);
892 pdata
->is_ar724x
= 1;
893 if (ath79_soc
== ATH79_SOC_AR7240
)
894 pdata
->is_ar7240
= 1;
896 if (!pdata
->fifo_cfg1
)
897 pdata
->fifo_cfg1
= 0x0010ffff;
898 if (!pdata
->fifo_cfg2
)
899 pdata
->fifo_cfg2
= 0x015500aa;
900 if (!pdata
->fifo_cfg3
)
901 pdata
->fifo_cfg3
= 0x01f00140;
904 case ATH79_SOC_AR9130
:
906 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
907 pdata
->set_speed
= ar91xx_set_speed_ge0
;
909 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
910 pdata
->set_speed
= ar91xx_set_speed_ge1
;
912 pdata
->is_ar91xx
= 1;
915 case ATH79_SOC_AR9132
:
917 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
918 pdata
->set_speed
= ar91xx_set_speed_ge0
;
920 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
921 pdata
->set_speed
= ar91xx_set_speed_ge1
;
923 pdata
->is_ar91xx
= 1;
927 case ATH79_SOC_AR9330
:
928 case ATH79_SOC_AR9331
:
930 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
931 AR933X_RESET_GE0_MDIO
;
932 pdata
->ddr_flush
= ar933x_ddr_flush_ge0
;
933 pdata
->set_speed
= ath79_set_speed_dummy
;
935 pdata
->phy_mask
= BIT(4);
937 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
938 AR933X_RESET_GE1_MDIO
;
939 pdata
->ddr_flush
= ar933x_ddr_flush_ge1
;
940 pdata
->set_speed
= ath79_set_speed_dummy
;
942 pdata
->speed
= SPEED_1000
;
943 pdata
->duplex
= DUPLEX_FULL
;
944 pdata
->switch_data
= &ath79_switch_data
;
946 ath79_switch_data
.phy_poll_mask
|= BIT(4);
950 pdata
->is_ar724x
= 1;
952 if (!pdata
->fifo_cfg1
)
953 pdata
->fifo_cfg1
= 0x0010ffff;
954 if (!pdata
->fifo_cfg2
)
955 pdata
->fifo_cfg2
= 0x015500aa;
956 if (!pdata
->fifo_cfg3
)
957 pdata
->fifo_cfg3
= 0x01f00140;
960 case ATH79_SOC_AR9341
:
961 case ATH79_SOC_AR9342
:
962 case ATH79_SOC_AR9344
:
964 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
965 AR934X_RESET_GE0_MDIO
;
966 pdata
->set_speed
= ar934x_set_speed_ge0
;
968 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
969 AR934X_RESET_GE1_MDIO
;
970 pdata
->set_speed
= ath79_set_speed_dummy
;
972 pdata
->switch_data
= &ath79_switch_data
;
974 /* reset the built-in switch */
975 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
976 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
979 pdata
->ddr_flush
= ath79_ddr_no_flush
;
981 pdata
->is_ar724x
= 1;
983 pdata
->max_frame_len
= SZ_16K
- 1;
984 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
986 if (!pdata
->fifo_cfg1
)
987 pdata
->fifo_cfg1
= 0x0010ffff;
988 if (!pdata
->fifo_cfg2
)
989 pdata
->fifo_cfg2
= 0x015500aa;
990 if (!pdata
->fifo_cfg3
)
991 pdata
->fifo_cfg3
= 0x01f00140;
994 case ATH79_SOC_QCA9533
:
996 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
997 AR933X_RESET_GE0_MDIO
;
998 pdata
->set_speed
= ath79_set_speed_dummy
;
1000 pdata
->phy_mask
= BIT(4);
1002 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
1003 AR933X_RESET_GE1_MDIO
;
1004 pdata
->set_speed
= ath79_set_speed_dummy
;
1006 pdata
->speed
= SPEED_1000
;
1007 pdata
->duplex
= DUPLEX_FULL
;
1008 pdata
->switch_data
= &ath79_switch_data
;
1010 ath79_switch_data
.phy_poll_mask
|= BIT(4);
1013 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1014 pdata
->has_gbit
= 1;
1015 pdata
->is_ar724x
= 1;
1017 if (!pdata
->fifo_cfg1
)
1018 pdata
->fifo_cfg1
= 0x0010ffff;
1019 if (!pdata
->fifo_cfg2
)
1020 pdata
->fifo_cfg2
= 0x015500aa;
1021 if (!pdata
->fifo_cfg3
)
1022 pdata
->fifo_cfg3
= 0x01f00140;
1025 case ATH79_SOC_QCA9556
:
1026 case ATH79_SOC_QCA9558
:
1028 pdata
->reset_bit
= QCA955X_RESET_GE0_MAC
|
1029 QCA955X_RESET_GE0_MDIO
;
1030 pdata
->set_speed
= qca955x_set_speed_xmii
;
1032 pdata
->reset_bit
= QCA955X_RESET_GE1_MAC
|
1033 QCA955X_RESET_GE1_MDIO
;
1034 pdata
->set_speed
= qca955x_set_speed_sgmii
;
1037 pdata
->ddr_flush
= ath79_ddr_no_flush
;
1038 pdata
->has_gbit
= 1;
1039 pdata
->is_ar724x
= 1;
1042 * Limit the maximum frame length to 4095 bytes.
1043 * Although the documentation says that the hardware
1044 * limit is 16383 bytes but that does not work in
1045 * practice. It seems that the hardware only updates
1046 * the lowest 12 bits of the packet length field
1047 * in the RX descriptor.
1049 pdata
->max_frame_len
= SZ_4K
- 1;
1050 pdata
->desc_pktlen_mask
= SZ_16K
- 1;
1052 if (!pdata
->fifo_cfg1
)
1053 pdata
->fifo_cfg1
= 0x0010ffff;
1054 if (!pdata
->fifo_cfg2
)
1055 pdata
->fifo_cfg2
= 0x015500aa;
1056 if (!pdata
->fifo_cfg3
)
1057 pdata
->fifo_cfg3
= 0x01f00140;
1064 switch (pdata
->phy_if_mode
) {
1065 case PHY_INTERFACE_MODE_GMII
:
1066 case PHY_INTERFACE_MODE_RGMII
:
1067 case PHY_INTERFACE_MODE_SGMII
:
1068 if (!pdata
->has_gbit
) {
1069 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
1078 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
1079 random_ether_addr(pdata
->mac_addr
);
1081 "ar71xx: using random MAC address for eth%d\n",
1082 ath79_eth_instance
);
1085 if (pdata
->mii_bus_dev
== NULL
) {
1086 switch (ath79_soc
) {
1087 case ATH79_SOC_AR9341
:
1088 case ATH79_SOC_AR9342
:
1089 case ATH79_SOC_AR9344
:
1091 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1093 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1096 case ATH79_SOC_AR7241
:
1097 case ATH79_SOC_AR9330
:
1098 case ATH79_SOC_AR9331
:
1099 case ATH79_SOC_QCA9533
:
1100 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
1103 case ATH79_SOC_QCA9556
:
1104 case ATH79_SOC_QCA9558
:
1105 /* don't assign any MDIO device by default */
1109 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
1114 /* Reset the device */
1115 ath79_device_reset_set(pdata
->reset_bit
);
1118 ath79_device_reset_clear(pdata
->reset_bit
);
1121 platform_device_register(pdev
);
1122 ath79_eth_instance
++;
1125 void __init
ath79_set_mac_base(unsigned char *mac
)
1127 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
1130 void __init
ath79_parse_ascii_mac(char *mac_str
, u8
*mac
)
1134 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1135 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1138 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1139 &mac
[0], &mac
[1], &mac
[2], &mac
[3], &mac
[4], &mac
[5]);
1141 if (t
!= ETH_ALEN
|| !is_valid_ether_addr(mac
)) {
1142 memset(mac
, 0, ETH_ALEN
);
1143 printk(KERN_DEBUG
"ar71xx: invalid mac address \"%s\"\n",
1148 static void __init
ath79_set_mac_base_ascii(char *str
)
1152 ath79_parse_ascii_mac(str
, mac
);
1153 ath79_set_mac_base(mac
);
1156 static int __init
ath79_ethaddr_setup(char *str
)
1158 ath79_set_mac_base_ascii(str
);
1161 __setup("ethaddr=", ath79_ethaddr_setup
);
1163 static int __init
ath79_kmac_setup(char *str
)
1165 ath79_set_mac_base_ascii(str
);
1168 __setup("kmac=", ath79_kmac_setup
);
1170 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
1178 if (!src
|| !is_valid_ether_addr(src
)) {
1179 memset(dst
, '\0', ETH_ALEN
);
1183 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1189 dst
[3] = (t
>> 16) & 0xff;
1190 dst
[4] = (t
>> 8) & 0xff;
1194 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
1201 if (!src
|| !is_valid_ether_addr(src
)) {
1202 memset(dst
, '\0', ETH_ALEN
);
1206 for (i
= 0; i
< ETH_ALEN
; i
++)