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[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
26 #include <asm/mach-ath79/irq.h>
27
28 #include "common.h"
29 #include "dev-eth.h"
30
31 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32
33 static struct resource ath79_mdio0_resources[] = {
34 {
35 .name = "mdio_base",
36 .flags = IORESOURCE_MEM,
37 .start = AR71XX_GE0_BASE,
38 .end = AR71XX_GE0_BASE + 0x200 - 1,
39 }
40 };
41
42 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43
44 struct platform_device ath79_mdio0_device = {
45 .name = "ag71xx-mdio",
46 .id = 0,
47 .resource = ath79_mdio0_resources,
48 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .dev = {
50 .platform_data = &ath79_mdio0_data,
51 },
52 };
53
54 static struct resource ath79_mdio1_resources[] = {
55 {
56 .name = "mdio_base",
57 .flags = IORESOURCE_MEM,
58 .start = AR71XX_GE1_BASE,
59 .end = AR71XX_GE1_BASE + 0x200 - 1,
60 }
61 };
62
63 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64
65 struct platform_device ath79_mdio1_device = {
66 .name = "ag71xx-mdio",
67 .id = 1,
68 .resource = ath79_mdio1_resources,
69 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .dev = {
71 .platform_data = &ath79_mdio1_data,
72 },
73 };
74
75 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
76 {
77 void __iomem *base;
78 u32 t;
79
80 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81
82 t = __raw_readl(base + cfg_reg);
83 t &= ~(3 << shift);
84 t |= (2 << shift);
85 __raw_writel(t, base + cfg_reg);
86 udelay(100);
87
88 __raw_writel(pll_val, base + pll_reg);
89
90 t |= (3 << shift);
91 __raw_writel(t, base + cfg_reg);
92 udelay(100);
93
94 t &= ~(3 << shift);
95 __raw_writel(t, base + cfg_reg);
96 udelay(100);
97
98 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
99 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
100
101 iounmap(base);
102 }
103
104 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
105 unsigned int mii_if)
106 {
107 void __iomem *base;
108 u32 t;
109
110 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111
112 t = __raw_readl(base + reg);
113 t &= ~(AR71XX_MII_CTRL_IF_MASK);
114 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
115 __raw_writel(t, base + reg);
116
117 iounmap(base);
118 }
119
120 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
121 {
122 void __iomem *base;
123 unsigned int mii_speed;
124 u32 t;
125
126 switch (speed) {
127 case SPEED_10:
128 mii_speed = AR71XX_MII_CTRL_SPEED_10;
129 break;
130 case SPEED_100:
131 mii_speed = AR71XX_MII_CTRL_SPEED_100;
132 break;
133 case SPEED_1000:
134 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
135 break;
136 default:
137 BUG();
138 }
139
140 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141
142 t = __raw_readl(base + reg);
143 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
144 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
145 __raw_writel(t, base + reg);
146
147 iounmap(base);
148 }
149
150 static unsigned long ar934x_get_mdio_ref_clock(void)
151 {
152 void __iomem *base;
153 unsigned long ret;
154 u32 t;
155
156 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
157
158 ret = 0;
159 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
160 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
161 ret = 100 * 1000 * 1000;
162 } else {
163 struct clk *clk;
164
165 clk = clk_get(NULL, "ref");
166 if (!IS_ERR(clk))
167 ret = clk_get_rate(clk);
168 }
169
170 iounmap(base);
171
172 return ret;
173 }
174
175 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
176 {
177 struct platform_device *mdio_dev;
178 struct ag71xx_mdio_platform_data *mdio_data;
179 unsigned int max_id;
180
181 if (ath79_soc == ATH79_SOC_AR9341 ||
182 ath79_soc == ATH79_SOC_AR9342 ||
183 ath79_soc == ATH79_SOC_AR9344 ||
184 ath79_soc == ATH79_SOC_QCA9556 ||
185 ath79_soc == ATH79_SOC_QCA9558)
186 max_id = 1;
187 else
188 max_id = 0;
189
190 if (id > max_id) {
191 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
192 return;
193 }
194
195 switch (ath79_soc) {
196 case ATH79_SOC_AR7241:
197 case ATH79_SOC_AR9330:
198 case ATH79_SOC_AR9331:
199 mdio_dev = &ath79_mdio1_device;
200 mdio_data = &ath79_mdio1_data;
201 break;
202
203 case ATH79_SOC_AR9341:
204 case ATH79_SOC_AR9342:
205 case ATH79_SOC_AR9344:
206 case ATH79_SOC_QCA9556:
207 case ATH79_SOC_QCA9558:
208 if (id == 0) {
209 mdio_dev = &ath79_mdio0_device;
210 mdio_data = &ath79_mdio0_data;
211 } else {
212 mdio_dev = &ath79_mdio1_device;
213 mdio_data = &ath79_mdio1_data;
214 }
215 break;
216
217 case ATH79_SOC_AR7242:
218 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
219 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
220 AR71XX_ETH0_PLL_SHIFT);
221 /* fall through */
222 default:
223 mdio_dev = &ath79_mdio0_device;
224 mdio_data = &ath79_mdio0_data;
225 break;
226 }
227
228 mdio_data->phy_mask = phy_mask;
229
230 switch (ath79_soc) {
231 case ATH79_SOC_AR7240:
232 mdio_data->is_ar7240 = 1;
233 /* fall through */
234 case ATH79_SOC_AR7241:
235 mdio_data->builtin_switch = 1;
236 break;
237
238 case ATH79_SOC_AR9330:
239 mdio_data->is_ar9330 = 1;
240 /* fall through */
241 case ATH79_SOC_AR9331:
242 mdio_data->builtin_switch = 1;
243 break;
244
245 case ATH79_SOC_AR9341:
246 case ATH79_SOC_AR9342:
247 case ATH79_SOC_AR9344:
248 if (id == 1) {
249 mdio_data->builtin_switch = 1;
250 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
251 mdio_data->mdio_clock = 6250000;
252 }
253 mdio_data->is_ar934x = 1;
254 break;
255
256 case ATH79_SOC_QCA9558:
257 if (id == 1)
258 mdio_data->builtin_switch = 1;
259 mdio_data->is_ar934x = 1;
260 break;
261
262 case ATH79_SOC_QCA9556:
263 mdio_data->is_ar934x = 1;
264 break;
265
266 default:
267 break;
268 }
269
270 platform_device_register(mdio_dev);
271 }
272
273 struct ath79_eth_pll_data ath79_eth0_pll_data;
274 struct ath79_eth_pll_data ath79_eth1_pll_data;
275
276 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
277 {
278 struct ath79_eth_pll_data *pll_data;
279 u32 pll_val;
280
281 switch (mac) {
282 case 0:
283 pll_data = &ath79_eth0_pll_data;
284 break;
285 case 1:
286 pll_data = &ath79_eth1_pll_data;
287 break;
288 default:
289 BUG();
290 }
291
292 switch (speed) {
293 case SPEED_10:
294 pll_val = pll_data->pll_10;
295 break;
296 case SPEED_100:
297 pll_val = pll_data->pll_100;
298 break;
299 case SPEED_1000:
300 pll_val = pll_data->pll_1000;
301 break;
302 default:
303 BUG();
304 }
305
306 return pll_val;
307 }
308
309 static void ath79_set_speed_ge0(int speed)
310 {
311 u32 val = ath79_get_eth_pll(0, speed);
312
313 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
314 val, AR71XX_ETH0_PLL_SHIFT);
315 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
316 }
317
318 static void ath79_set_speed_ge1(int speed)
319 {
320 u32 val = ath79_get_eth_pll(1, speed);
321
322 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
323 val, AR71XX_ETH1_PLL_SHIFT);
324 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
325 }
326
327 static void ar7242_set_speed_ge0(int speed)
328 {
329 u32 val = ath79_get_eth_pll(0, speed);
330 void __iomem *base;
331
332 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
333 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
334 iounmap(base);
335 }
336
337 static void ar91xx_set_speed_ge0(int speed)
338 {
339 u32 val = ath79_get_eth_pll(0, speed);
340
341 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
342 val, AR913X_ETH0_PLL_SHIFT);
343 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
344 }
345
346 static void ar91xx_set_speed_ge1(int speed)
347 {
348 u32 val = ath79_get_eth_pll(1, speed);
349
350 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
351 val, AR913X_ETH1_PLL_SHIFT);
352 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
353 }
354
355 static void ar934x_set_speed_ge0(int speed)
356 {
357 void __iomem *base;
358 u32 val = ath79_get_eth_pll(0, speed);
359
360 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
361 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
362 iounmap(base);
363 }
364
365 static void qca955x_set_speed_xmii(int speed)
366 {
367 void __iomem *base;
368 u32 val = ath79_get_eth_pll(0, speed);
369
370 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
371 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
372 iounmap(base);
373 }
374
375 static void qca955x_set_speed_sgmii(int speed)
376 {
377 void __iomem *base;
378 u32 val = ath79_get_eth_pll(1, speed);
379
380 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
381 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
382 iounmap(base);
383 }
384
385 static void ath79_set_speed_dummy(int speed)
386 {
387 }
388
389 static void ath79_ddr_no_flush(void)
390 {
391 }
392
393 static void ath79_ddr_flush_ge0(void)
394 {
395 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
396 }
397
398 static void ath79_ddr_flush_ge1(void)
399 {
400 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
401 }
402
403 static void ar724x_ddr_flush_ge0(void)
404 {
405 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
406 }
407
408 static void ar724x_ddr_flush_ge1(void)
409 {
410 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
411 }
412
413 static void ar91xx_ddr_flush_ge0(void)
414 {
415 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
416 }
417
418 static void ar91xx_ddr_flush_ge1(void)
419 {
420 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
421 }
422
423 static void ar933x_ddr_flush_ge0(void)
424 {
425 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
426 }
427
428 static void ar933x_ddr_flush_ge1(void)
429 {
430 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
431 }
432
433 static struct resource ath79_eth0_resources[] = {
434 {
435 .name = "mac_base",
436 .flags = IORESOURCE_MEM,
437 .start = AR71XX_GE0_BASE,
438 .end = AR71XX_GE0_BASE + 0x200 - 1,
439 }, {
440 .name = "mac_irq",
441 .flags = IORESOURCE_IRQ,
442 .start = ATH79_CPU_IRQ_GE0,
443 .end = ATH79_CPU_IRQ_GE0,
444 },
445 };
446
447 struct ag71xx_platform_data ath79_eth0_data = {
448 .reset_bit = AR71XX_RESET_GE0_MAC,
449 };
450
451 struct platform_device ath79_eth0_device = {
452 .name = "ag71xx",
453 .id = 0,
454 .resource = ath79_eth0_resources,
455 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
456 .dev = {
457 .platform_data = &ath79_eth0_data,
458 },
459 };
460
461 static struct resource ath79_eth1_resources[] = {
462 {
463 .name = "mac_base",
464 .flags = IORESOURCE_MEM,
465 .start = AR71XX_GE1_BASE,
466 .end = AR71XX_GE1_BASE + 0x200 - 1,
467 }, {
468 .name = "mac_irq",
469 .flags = IORESOURCE_IRQ,
470 .start = ATH79_CPU_IRQ_GE1,
471 .end = ATH79_CPU_IRQ_GE1,
472 },
473 };
474
475 struct ag71xx_platform_data ath79_eth1_data = {
476 .reset_bit = AR71XX_RESET_GE1_MAC,
477 };
478
479 struct platform_device ath79_eth1_device = {
480 .name = "ag71xx",
481 .id = 1,
482 .resource = ath79_eth1_resources,
483 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
484 .dev = {
485 .platform_data = &ath79_eth1_data,
486 },
487 };
488
489 struct ag71xx_switch_platform_data ath79_switch_data;
490
491 #define AR71XX_PLL_VAL_1000 0x00110000
492 #define AR71XX_PLL_VAL_100 0x00001099
493 #define AR71XX_PLL_VAL_10 0x00991099
494
495 #define AR724X_PLL_VAL_1000 0x00110000
496 #define AR724X_PLL_VAL_100 0x00001099
497 #define AR724X_PLL_VAL_10 0x00991099
498
499 #define AR7242_PLL_VAL_1000 0x16000000
500 #define AR7242_PLL_VAL_100 0x00000101
501 #define AR7242_PLL_VAL_10 0x00001616
502
503 #define AR913X_PLL_VAL_1000 0x1a000000
504 #define AR913X_PLL_VAL_100 0x13000a44
505 #define AR913X_PLL_VAL_10 0x00441099
506
507 #define AR933X_PLL_VAL_1000 0x00110000
508 #define AR933X_PLL_VAL_100 0x00001099
509 #define AR933X_PLL_VAL_10 0x00991099
510
511 #define AR934X_PLL_VAL_1000 0x16000000
512 #define AR934X_PLL_VAL_100 0x00000101
513 #define AR934X_PLL_VAL_10 0x00001616
514
515 static void __init ath79_init_eth_pll_data(unsigned int id)
516 {
517 struct ath79_eth_pll_data *pll_data;
518 u32 pll_10, pll_100, pll_1000;
519
520 switch (id) {
521 case 0:
522 pll_data = &ath79_eth0_pll_data;
523 break;
524 case 1:
525 pll_data = &ath79_eth1_pll_data;
526 break;
527 default:
528 BUG();
529 }
530
531 switch (ath79_soc) {
532 case ATH79_SOC_AR7130:
533 case ATH79_SOC_AR7141:
534 case ATH79_SOC_AR7161:
535 pll_10 = AR71XX_PLL_VAL_10;
536 pll_100 = AR71XX_PLL_VAL_100;
537 pll_1000 = AR71XX_PLL_VAL_1000;
538 break;
539
540 case ATH79_SOC_AR7240:
541 case ATH79_SOC_AR7241:
542 pll_10 = AR724X_PLL_VAL_10;
543 pll_100 = AR724X_PLL_VAL_100;
544 pll_1000 = AR724X_PLL_VAL_1000;
545 break;
546
547 case ATH79_SOC_AR7242:
548 pll_10 = AR7242_PLL_VAL_10;
549 pll_100 = AR7242_PLL_VAL_100;
550 pll_1000 = AR7242_PLL_VAL_1000;
551 break;
552
553 case ATH79_SOC_AR9130:
554 case ATH79_SOC_AR9132:
555 pll_10 = AR913X_PLL_VAL_10;
556 pll_100 = AR913X_PLL_VAL_100;
557 pll_1000 = AR913X_PLL_VAL_1000;
558 break;
559
560 case ATH79_SOC_AR9330:
561 case ATH79_SOC_AR9331:
562 pll_10 = AR933X_PLL_VAL_10;
563 pll_100 = AR933X_PLL_VAL_100;
564 pll_1000 = AR933X_PLL_VAL_1000;
565 break;
566
567 case ATH79_SOC_AR9341:
568 case ATH79_SOC_AR9342:
569 case ATH79_SOC_AR9344:
570 case ATH79_SOC_QCA9556:
571 case ATH79_SOC_QCA9558:
572 pll_10 = AR934X_PLL_VAL_10;
573 pll_100 = AR934X_PLL_VAL_100;
574 pll_1000 = AR934X_PLL_VAL_1000;
575 break;
576
577 default:
578 BUG();
579 }
580
581 if (!pll_data->pll_10)
582 pll_data->pll_10 = pll_10;
583
584 if (!pll_data->pll_100)
585 pll_data->pll_100 = pll_100;
586
587 if (!pll_data->pll_1000)
588 pll_data->pll_1000 = pll_1000;
589 }
590
591 static int __init ath79_setup_phy_if_mode(unsigned int id,
592 struct ag71xx_platform_data *pdata)
593 {
594 unsigned int mii_if;
595
596 switch (id) {
597 case 0:
598 switch (ath79_soc) {
599 case ATH79_SOC_AR7130:
600 case ATH79_SOC_AR7141:
601 case ATH79_SOC_AR7161:
602 case ATH79_SOC_AR9130:
603 case ATH79_SOC_AR9132:
604 switch (pdata->phy_if_mode) {
605 case PHY_INTERFACE_MODE_MII:
606 mii_if = AR71XX_MII0_CTRL_IF_MII;
607 break;
608 case PHY_INTERFACE_MODE_GMII:
609 mii_if = AR71XX_MII0_CTRL_IF_GMII;
610 break;
611 case PHY_INTERFACE_MODE_RGMII:
612 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
613 break;
614 case PHY_INTERFACE_MODE_RMII:
615 mii_if = AR71XX_MII0_CTRL_IF_RMII;
616 break;
617 default:
618 return -EINVAL;
619 }
620 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
621 break;
622
623 case ATH79_SOC_AR7240:
624 case ATH79_SOC_AR7241:
625 case ATH79_SOC_AR9330:
626 case ATH79_SOC_AR9331:
627 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
628 break;
629
630 case ATH79_SOC_AR7242:
631 /* FIXME */
632
633 case ATH79_SOC_AR9341:
634 case ATH79_SOC_AR9342:
635 case ATH79_SOC_AR9344:
636 switch (pdata->phy_if_mode) {
637 case PHY_INTERFACE_MODE_MII:
638 case PHY_INTERFACE_MODE_GMII:
639 case PHY_INTERFACE_MODE_RGMII:
640 case PHY_INTERFACE_MODE_RMII:
641 break;
642 default:
643 return -EINVAL;
644 }
645 break;
646
647 case ATH79_SOC_QCA9556:
648 case ATH79_SOC_QCA9558:
649 switch (pdata->phy_if_mode) {
650 case PHY_INTERFACE_MODE_MII:
651 case PHY_INTERFACE_MODE_RGMII:
652 case PHY_INTERFACE_MODE_SGMII:
653 break;
654 default:
655 return -EINVAL;
656 }
657 break;
658
659 default:
660 BUG();
661 }
662 break;
663 case 1:
664 switch (ath79_soc) {
665 case ATH79_SOC_AR7130:
666 case ATH79_SOC_AR7141:
667 case ATH79_SOC_AR7161:
668 case ATH79_SOC_AR9130:
669 case ATH79_SOC_AR9132:
670 switch (pdata->phy_if_mode) {
671 case PHY_INTERFACE_MODE_RMII:
672 mii_if = AR71XX_MII1_CTRL_IF_RMII;
673 break;
674 case PHY_INTERFACE_MODE_RGMII:
675 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
676 break;
677 default:
678 return -EINVAL;
679 }
680 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
681 break;
682
683 case ATH79_SOC_AR7240:
684 case ATH79_SOC_AR7241:
685 case ATH79_SOC_AR9330:
686 case ATH79_SOC_AR9331:
687 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
688 break;
689
690 case ATH79_SOC_AR7242:
691 /* FIXME */
692
693 case ATH79_SOC_AR9341:
694 case ATH79_SOC_AR9342:
695 case ATH79_SOC_AR9344:
696 switch (pdata->phy_if_mode) {
697 case PHY_INTERFACE_MODE_MII:
698 case PHY_INTERFACE_MODE_GMII:
699 break;
700 default:
701 return -EINVAL;
702 }
703 break;
704
705 case ATH79_SOC_QCA9556:
706 case ATH79_SOC_QCA9558:
707 switch (pdata->phy_if_mode) {
708 case PHY_INTERFACE_MODE_MII:
709 case PHY_INTERFACE_MODE_RGMII:
710 case PHY_INTERFACE_MODE_SGMII:
711 break;
712 default:
713 return -EINVAL;
714 }
715 break;
716
717 default:
718 BUG();
719 }
720 break;
721 }
722
723 return 0;
724 }
725
726 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
727 {
728 void __iomem *base;
729 u32 t;
730
731 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
732
733 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
734 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
735 if (mac)
736 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
737 if (mdio)
738 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
739 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
740
741 iounmap(base);
742 }
743
744 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
745 {
746 void __iomem *base;
747 u32 t;
748
749 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
750
751 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
752
753 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
754 AR934X_ETH_CFG_MII_GMAC0 |
755 AR934X_ETH_CFG_GMII_GMAC0 |
756 AR934X_ETH_CFG_SW_ONLY_MODE |
757 AR934X_ETH_CFG_SW_PHY_SWAP);
758
759 t |= mask;
760
761 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
762 /* flush write */
763 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
764
765 iounmap(base);
766 }
767
768 static int ath79_eth_instance __initdata;
769 void __init ath79_register_eth(unsigned int id)
770 {
771 struct platform_device *pdev;
772 struct ag71xx_platform_data *pdata;
773 int err;
774
775 if (id > 1) {
776 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
777 return;
778 }
779
780 ath79_init_eth_pll_data(id);
781
782 if (id == 0)
783 pdev = &ath79_eth0_device;
784 else
785 pdev = &ath79_eth1_device;
786
787 pdata = pdev->dev.platform_data;
788
789 err = ath79_setup_phy_if_mode(id, pdata);
790 if (err) {
791 printk(KERN_ERR
792 "ar71xx: invalid PHY interface mode for GE%u\n", id);
793 return;
794 }
795
796 switch (ath79_soc) {
797 case ATH79_SOC_AR7130:
798 if (id == 0) {
799 pdata->ddr_flush = ath79_ddr_flush_ge0;
800 pdata->set_speed = ath79_set_speed_ge0;
801 } else {
802 pdata->ddr_flush = ath79_ddr_flush_ge1;
803 pdata->set_speed = ath79_set_speed_ge1;
804 }
805 break;
806
807 case ATH79_SOC_AR7141:
808 case ATH79_SOC_AR7161:
809 if (id == 0) {
810 pdata->ddr_flush = ath79_ddr_flush_ge0;
811 pdata->set_speed = ath79_set_speed_ge0;
812 } else {
813 pdata->ddr_flush = ath79_ddr_flush_ge1;
814 pdata->set_speed = ath79_set_speed_ge1;
815 }
816 pdata->has_gbit = 1;
817 break;
818
819 case ATH79_SOC_AR7242:
820 if (id == 0) {
821 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
822 AR71XX_RESET_GE0_PHY;
823 pdata->ddr_flush = ar724x_ddr_flush_ge0;
824 pdata->set_speed = ar7242_set_speed_ge0;
825 } else {
826 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
827 AR71XX_RESET_GE1_PHY;
828 pdata->ddr_flush = ar724x_ddr_flush_ge1;
829 pdata->set_speed = ath79_set_speed_dummy;
830 }
831 pdata->has_gbit = 1;
832 pdata->is_ar724x = 1;
833
834 if (!pdata->fifo_cfg1)
835 pdata->fifo_cfg1 = 0x0010ffff;
836 if (!pdata->fifo_cfg2)
837 pdata->fifo_cfg2 = 0x015500aa;
838 if (!pdata->fifo_cfg3)
839 pdata->fifo_cfg3 = 0x01f00140;
840 break;
841
842 case ATH79_SOC_AR7241:
843 if (id == 0)
844 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
845 else
846 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
847 /* fall through */
848 case ATH79_SOC_AR7240:
849 if (id == 0) {
850 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
851 pdata->ddr_flush = ar724x_ddr_flush_ge0;
852 pdata->set_speed = ath79_set_speed_dummy;
853
854 pdata->phy_mask = BIT(4);
855 } else {
856 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
857 pdata->ddr_flush = ar724x_ddr_flush_ge1;
858 pdata->set_speed = ath79_set_speed_dummy;
859
860 pdata->speed = SPEED_1000;
861 pdata->duplex = DUPLEX_FULL;
862 pdata->switch_data = &ath79_switch_data;
863
864 ath79_switch_data.phy_poll_mask |= BIT(4);
865 }
866 pdata->has_gbit = 1;
867 pdata->is_ar724x = 1;
868 if (ath79_soc == ATH79_SOC_AR7240)
869 pdata->is_ar7240 = 1;
870
871 if (!pdata->fifo_cfg1)
872 pdata->fifo_cfg1 = 0x0010ffff;
873 if (!pdata->fifo_cfg2)
874 pdata->fifo_cfg2 = 0x015500aa;
875 if (!pdata->fifo_cfg3)
876 pdata->fifo_cfg3 = 0x01f00140;
877 break;
878
879 case ATH79_SOC_AR9130:
880 if (id == 0) {
881 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
882 pdata->set_speed = ar91xx_set_speed_ge0;
883 } else {
884 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
885 pdata->set_speed = ar91xx_set_speed_ge1;
886 }
887 pdata->is_ar91xx = 1;
888 break;
889
890 case ATH79_SOC_AR9132:
891 if (id == 0) {
892 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
893 pdata->set_speed = ar91xx_set_speed_ge0;
894 } else {
895 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
896 pdata->set_speed = ar91xx_set_speed_ge1;
897 }
898 pdata->is_ar91xx = 1;
899 pdata->has_gbit = 1;
900 break;
901
902 case ATH79_SOC_AR9330:
903 case ATH79_SOC_AR9331:
904 if (id == 0) {
905 pdata->reset_bit = AR933X_RESET_GE0_MAC |
906 AR933X_RESET_GE0_MDIO;
907 pdata->ddr_flush = ar933x_ddr_flush_ge0;
908 pdata->set_speed = ath79_set_speed_dummy;
909
910 pdata->phy_mask = BIT(4);
911 } else {
912 pdata->reset_bit = AR933X_RESET_GE1_MAC |
913 AR933X_RESET_GE1_MDIO;
914 pdata->ddr_flush = ar933x_ddr_flush_ge1;
915 pdata->set_speed = ath79_set_speed_dummy;
916
917 pdata->speed = SPEED_1000;
918 pdata->duplex = DUPLEX_FULL;
919 pdata->switch_data = &ath79_switch_data;
920
921 ath79_switch_data.phy_poll_mask |= BIT(4);
922 }
923
924 pdata->has_gbit = 1;
925 pdata->is_ar724x = 1;
926
927 if (!pdata->fifo_cfg1)
928 pdata->fifo_cfg1 = 0x0010ffff;
929 if (!pdata->fifo_cfg2)
930 pdata->fifo_cfg2 = 0x015500aa;
931 if (!pdata->fifo_cfg3)
932 pdata->fifo_cfg3 = 0x01f00140;
933 break;
934
935 case ATH79_SOC_AR9341:
936 case ATH79_SOC_AR9342:
937 case ATH79_SOC_AR9344:
938 if (id == 0) {
939 pdata->reset_bit = AR934X_RESET_GE0_MAC |
940 AR934X_RESET_GE0_MDIO;
941 pdata->set_speed = ar934x_set_speed_ge0;
942 } else {
943 pdata->reset_bit = AR934X_RESET_GE1_MAC |
944 AR934X_RESET_GE1_MDIO;
945 pdata->set_speed = ath79_set_speed_dummy;
946
947 pdata->switch_data = &ath79_switch_data;
948
949 /* reset the built-in switch */
950 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
951 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
952 }
953
954 pdata->ddr_flush = ath79_ddr_no_flush;
955 pdata->has_gbit = 1;
956 pdata->is_ar724x = 1;
957
958 if (!pdata->fifo_cfg1)
959 pdata->fifo_cfg1 = 0x0010ffff;
960 if (!pdata->fifo_cfg2)
961 pdata->fifo_cfg2 = 0x015500aa;
962 if (!pdata->fifo_cfg3)
963 pdata->fifo_cfg3 = 0x01f00140;
964 break;
965
966 case ATH79_SOC_QCA9556:
967 case ATH79_SOC_QCA9558:
968 if (id == 0) {
969 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
970 QCA955X_RESET_GE0_MDIO;
971 pdata->set_speed = qca955x_set_speed_xmii;
972 } else {
973 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
974 QCA955X_RESET_GE1_MDIO;
975 pdata->set_speed = qca955x_set_speed_sgmii;
976 }
977
978 pdata->ddr_flush = ath79_ddr_no_flush;
979 pdata->has_gbit = 1;
980 pdata->is_ar724x = 1;
981
982 if (!pdata->fifo_cfg1)
983 pdata->fifo_cfg1 = 0x0010ffff;
984 if (!pdata->fifo_cfg2)
985 pdata->fifo_cfg2 = 0x015500aa;
986 if (!pdata->fifo_cfg3)
987 pdata->fifo_cfg3 = 0x01f00140;
988 break;
989
990 default:
991 BUG();
992 }
993
994 switch (pdata->phy_if_mode) {
995 case PHY_INTERFACE_MODE_GMII:
996 case PHY_INTERFACE_MODE_RGMII:
997 case PHY_INTERFACE_MODE_SGMII:
998 if (!pdata->has_gbit) {
999 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1000 id);
1001 return;
1002 }
1003 /* fallthrough */
1004 default:
1005 break;
1006 }
1007
1008 if (!is_valid_ether_addr(pdata->mac_addr)) {
1009 random_ether_addr(pdata->mac_addr);
1010 printk(KERN_DEBUG
1011 "ar71xx: using random MAC address for eth%d\n",
1012 ath79_eth_instance);
1013 }
1014
1015 if (pdata->mii_bus_dev == NULL) {
1016 switch (ath79_soc) {
1017 case ATH79_SOC_AR9341:
1018 case ATH79_SOC_AR9342:
1019 case ATH79_SOC_AR9344:
1020 if (id == 0)
1021 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1022 else
1023 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1024 break;
1025
1026 case ATH79_SOC_AR7241:
1027 case ATH79_SOC_AR9330:
1028 case ATH79_SOC_AR9331:
1029 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1030 break;
1031
1032 case ATH79_SOC_QCA9556:
1033 case ATH79_SOC_QCA9558:
1034 /* don't assign any MDIO device by default */
1035 break;
1036
1037 default:
1038 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1039 break;
1040 }
1041 }
1042
1043 /* Reset the device */
1044 ath79_device_reset_set(pdata->reset_bit);
1045 mdelay(100);
1046
1047 ath79_device_reset_clear(pdata->reset_bit);
1048 mdelay(100);
1049
1050 platform_device_register(pdev);
1051 ath79_eth_instance++;
1052 }
1053
1054 void __init ath79_set_mac_base(unsigned char *mac)
1055 {
1056 memcpy(ath79_mac_base, mac, ETH_ALEN);
1057 }
1058
1059 void __init ath79_parse_mac_addr(char *mac_str)
1060 {
1061 u8 tmp[ETH_ALEN];
1062 int t;
1063
1064 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1065 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1066
1067 if (t != ETH_ALEN)
1068 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1069 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1070
1071 if (t == ETH_ALEN)
1072 ath79_set_mac_base(tmp);
1073 else
1074 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1075 "\"%s\"\n", mac_str);
1076 }
1077
1078 static int __init ath79_ethaddr_setup(char *str)
1079 {
1080 ath79_parse_mac_addr(str);
1081 return 1;
1082 }
1083 __setup("ethaddr=", ath79_ethaddr_setup);
1084
1085 static int __init ath79_kmac_setup(char *str)
1086 {
1087 ath79_parse_mac_addr(str);
1088 return 1;
1089 }
1090 __setup("kmac=", ath79_kmac_setup);
1091
1092 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1093 int offset)
1094 {
1095 int t;
1096
1097 if (!dst)
1098 return;
1099
1100 if (!src || !is_valid_ether_addr(src)) {
1101 memset(dst, '\0', ETH_ALEN);
1102 return;
1103 }
1104
1105 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1106 t += offset;
1107
1108 dst[0] = src[0];
1109 dst[1] = src[1];
1110 dst[2] = src[2];
1111 dst[3] = (t >> 16) & 0xff;
1112 dst[4] = (t >> 8) & 0xff;
1113 dst[5] = t & 0xff;
1114 }
1115
1116 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1117 {
1118 int i;
1119
1120 if (!dst)
1121 return;
1122
1123 if (!src || !is_valid_ether_addr(src)) {
1124 memset(dst, '\0', ETH_ALEN);
1125 return;
1126 }
1127
1128 for (i = 0; i < ETH_ALEN; i++)
1129 dst[i] = src[i];
1130 dst[0] |= 0x02;
1131 }
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