2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
30 unsigned char ath79_mac_base
[ETH_ALEN
] __initdata
;
32 static struct resource ath79_mdio0_resources
[] = {
35 .flags
= IORESOURCE_MEM
,
36 .start
= AR71XX_GE0_BASE
,
37 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data
;
43 struct platform_device ath79_mdio0_device
= {
44 .name
= "ag71xx-mdio",
46 .resource
= ath79_mdio0_resources
,
47 .num_resources
= ARRAY_SIZE(ath79_mdio0_resources
),
49 .platform_data
= &ath79_mdio0_data
,
53 static struct resource ath79_mdio1_resources
[] = {
56 .flags
= IORESOURCE_MEM
,
57 .start
= AR71XX_GE1_BASE
,
58 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data
;
64 struct platform_device ath79_mdio1_device
= {
65 .name
= "ag71xx-mdio",
67 .resource
= ath79_mdio1_resources
,
68 .num_resources
= ARRAY_SIZE(ath79_mdio1_resources
),
70 .platform_data
= &ath79_mdio1_data
,
74 static void ath79_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
79 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
81 t
= __raw_readl(base
+ cfg_reg
);
84 __raw_writel(t
, base
+ cfg_reg
);
87 __raw_writel(pll_val
, base
+ pll_reg
);
90 __raw_writel(t
, base
+ cfg_reg
);
94 __raw_writel(t
, base
+ cfg_reg
);
97 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
103 static void __init
ath79_mii_ctrl_set_if(unsigned int reg
,
109 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
111 t
= __raw_readl(base
+ reg
);
112 t
&= ~(AR71XX_MII_CTRL_IF_MASK
);
113 t
|= (mii_if
& AR71XX_MII_CTRL_IF_MASK
);
114 __raw_writel(t
, base
+ reg
);
119 static void ath79_mii_ctrl_set_speed(unsigned int reg
, unsigned int speed
)
122 unsigned int mii_speed
;
127 mii_speed
= AR71XX_MII_CTRL_SPEED_10
;
130 mii_speed
= AR71XX_MII_CTRL_SPEED_100
;
133 mii_speed
= AR71XX_MII_CTRL_SPEED_1000
;
139 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
141 t
= __raw_readl(base
+ reg
);
142 t
&= ~(AR71XX_MII_CTRL_SPEED_MASK
<< AR71XX_MII_CTRL_SPEED_SHIFT
);
143 t
|= mii_speed
<< AR71XX_MII_CTRL_SPEED_SHIFT
;
144 __raw_writel(t
, base
+ reg
);
149 void __init
ath79_register_mdio(unsigned int id
, u32 phy_mask
)
151 struct platform_device
*mdio_dev
;
152 struct ag71xx_mdio_platform_data
*mdio_data
;
155 if (ath79_soc
== ATH79_SOC_AR9341
||
156 ath79_soc
== ATH79_SOC_AR9342
||
157 ath79_soc
== ATH79_SOC_AR9344
||
158 ath79_soc
== ATH79_SOC_QCA9558
)
164 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
169 case ATH79_SOC_AR7241
:
170 case ATH79_SOC_AR9330
:
171 case ATH79_SOC_AR9331
:
172 mdio_dev
= &ath79_mdio1_device
;
173 mdio_data
= &ath79_mdio1_data
;
176 case ATH79_SOC_AR9341
:
177 case ATH79_SOC_AR9342
:
178 case ATH79_SOC_AR9344
:
179 case ATH79_SOC_QCA9558
:
181 mdio_dev
= &ath79_mdio0_device
;
182 mdio_data
= &ath79_mdio0_data
;
184 mdio_dev
= &ath79_mdio1_device
;
185 mdio_data
= &ath79_mdio1_data
;
189 case ATH79_SOC_AR7242
:
190 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
191 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
192 AR71XX_ETH0_PLL_SHIFT
);
195 mdio_dev
= &ath79_mdio0_device
;
196 mdio_data
= &ath79_mdio0_data
;
200 mdio_data
->phy_mask
= phy_mask
;
203 case ATH79_SOC_AR7240
:
204 mdio_data
->is_ar7240
= 1;
206 case ATH79_SOC_AR7241
:
207 mdio_data
->builtin_switch
= 1;
210 case ATH79_SOC_AR9330
:
211 mdio_data
->is_ar9330
= 1;
213 case ATH79_SOC_AR9331
:
214 mdio_data
->builtin_switch
= 1;
217 case ATH79_SOC_AR9341
:
218 case ATH79_SOC_AR9342
:
219 case ATH79_SOC_AR9344
:
220 case ATH79_SOC_QCA9558
:
222 mdio_data
->builtin_switch
= 1;
223 mdio_data
->is_ar934x
= 1;
230 platform_device_register(mdio_dev
);
233 struct ath79_eth_pll_data ath79_eth0_pll_data
;
234 struct ath79_eth_pll_data ath79_eth1_pll_data
;
236 static u32
ath79_get_eth_pll(unsigned int mac
, int speed
)
238 struct ath79_eth_pll_data
*pll_data
;
243 pll_data
= &ath79_eth0_pll_data
;
246 pll_data
= &ath79_eth1_pll_data
;
254 pll_val
= pll_data
->pll_10
;
257 pll_val
= pll_data
->pll_100
;
260 pll_val
= pll_data
->pll_1000
;
269 static void ath79_set_speed_ge0(int speed
)
271 u32 val
= ath79_get_eth_pll(0, speed
);
273 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
274 val
, AR71XX_ETH0_PLL_SHIFT
);
275 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
278 static void ath79_set_speed_ge1(int speed
)
280 u32 val
= ath79_get_eth_pll(1, speed
);
282 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
283 val
, AR71XX_ETH1_PLL_SHIFT
);
284 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
287 static void ar7242_set_speed_ge0(int speed
)
289 u32 val
= ath79_get_eth_pll(0, speed
);
292 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
293 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
297 static void ar91xx_set_speed_ge0(int speed
)
299 u32 val
= ath79_get_eth_pll(0, speed
);
301 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH0_INT_CLOCK
,
302 val
, AR913X_ETH0_PLL_SHIFT
);
303 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL
, speed
);
306 static void ar91xx_set_speed_ge1(int speed
)
308 u32 val
= ath79_get_eth_pll(1, speed
);
310 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG
, AR913X_PLL_REG_ETH1_INT_CLOCK
,
311 val
, AR913X_ETH1_PLL_SHIFT
);
312 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL
, speed
);
315 static void ar934x_set_speed_ge0(int speed
)
318 u32 val
= ath79_get_eth_pll(0, speed
);
320 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
321 __raw_writel(val
, base
+ AR934X_PLL_ETH_XMII_CONTROL_REG
);
325 static void ath79_set_speed_dummy(int speed
)
329 static void ath79_ddr_no_flush(void)
333 static void ath79_ddr_flush_ge0(void)
335 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0
);
338 static void ath79_ddr_flush_ge1(void)
340 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1
);
343 static void ar724x_ddr_flush_ge0(void)
345 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0
);
348 static void ar724x_ddr_flush_ge1(void)
350 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1
);
353 static void ar91xx_ddr_flush_ge0(void)
355 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0
);
358 static void ar91xx_ddr_flush_ge1(void)
360 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1
);
363 static void ar933x_ddr_flush_ge0(void)
365 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0
);
368 static void ar933x_ddr_flush_ge1(void)
370 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1
);
373 static struct resource ath79_eth0_resources
[] = {
376 .flags
= IORESOURCE_MEM
,
377 .start
= AR71XX_GE0_BASE
,
378 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
381 .flags
= IORESOURCE_IRQ
,
382 .start
= ATH79_CPU_IRQ_GE0
,
383 .end
= ATH79_CPU_IRQ_GE0
,
387 struct ag71xx_platform_data ath79_eth0_data
= {
388 .reset_bit
= AR71XX_RESET_GE0_MAC
,
391 struct platform_device ath79_eth0_device
= {
394 .resource
= ath79_eth0_resources
,
395 .num_resources
= ARRAY_SIZE(ath79_eth0_resources
),
397 .platform_data
= &ath79_eth0_data
,
401 static struct resource ath79_eth1_resources
[] = {
404 .flags
= IORESOURCE_MEM
,
405 .start
= AR71XX_GE1_BASE
,
406 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
409 .flags
= IORESOURCE_IRQ
,
410 .start
= ATH79_CPU_IRQ_GE1
,
411 .end
= ATH79_CPU_IRQ_GE1
,
415 struct ag71xx_platform_data ath79_eth1_data
= {
416 .reset_bit
= AR71XX_RESET_GE1_MAC
,
419 struct platform_device ath79_eth1_device
= {
422 .resource
= ath79_eth1_resources
,
423 .num_resources
= ARRAY_SIZE(ath79_eth1_resources
),
425 .platform_data
= &ath79_eth1_data
,
429 struct ag71xx_switch_platform_data ath79_switch_data
;
431 #define AR71XX_PLL_VAL_1000 0x00110000
432 #define AR71XX_PLL_VAL_100 0x00001099
433 #define AR71XX_PLL_VAL_10 0x00991099
435 #define AR724X_PLL_VAL_1000 0x00110000
436 #define AR724X_PLL_VAL_100 0x00001099
437 #define AR724X_PLL_VAL_10 0x00991099
439 #define AR7242_PLL_VAL_1000 0x16000000
440 #define AR7242_PLL_VAL_100 0x00000101
441 #define AR7242_PLL_VAL_10 0x00001616
443 #define AR913X_PLL_VAL_1000 0x1a000000
444 #define AR913X_PLL_VAL_100 0x13000a44
445 #define AR913X_PLL_VAL_10 0x00441099
447 #define AR933X_PLL_VAL_1000 0x00110000
448 #define AR933X_PLL_VAL_100 0x00001099
449 #define AR933X_PLL_VAL_10 0x00991099
451 #define AR934X_PLL_VAL_1000 0x16000000
452 #define AR934X_PLL_VAL_100 0x00000101
453 #define AR934X_PLL_VAL_10 0x00001616
455 static void __init
ath79_init_eth_pll_data(unsigned int id
)
457 struct ath79_eth_pll_data
*pll_data
;
458 u32 pll_10
, pll_100
, pll_1000
;
462 pll_data
= &ath79_eth0_pll_data
;
465 pll_data
= &ath79_eth1_pll_data
;
472 case ATH79_SOC_AR7130
:
473 case ATH79_SOC_AR7141
:
474 case ATH79_SOC_AR7161
:
475 pll_10
= AR71XX_PLL_VAL_10
;
476 pll_100
= AR71XX_PLL_VAL_100
;
477 pll_1000
= AR71XX_PLL_VAL_1000
;
480 case ATH79_SOC_AR7240
:
481 case ATH79_SOC_AR7241
:
482 pll_10
= AR724X_PLL_VAL_10
;
483 pll_100
= AR724X_PLL_VAL_100
;
484 pll_1000
= AR724X_PLL_VAL_1000
;
487 case ATH79_SOC_AR7242
:
488 pll_10
= AR7242_PLL_VAL_10
;
489 pll_100
= AR7242_PLL_VAL_100
;
490 pll_1000
= AR7242_PLL_VAL_1000
;
493 case ATH79_SOC_AR9130
:
494 case ATH79_SOC_AR9132
:
495 pll_10
= AR913X_PLL_VAL_10
;
496 pll_100
= AR913X_PLL_VAL_100
;
497 pll_1000
= AR913X_PLL_VAL_1000
;
500 case ATH79_SOC_AR9330
:
501 case ATH79_SOC_AR9331
:
502 pll_10
= AR933X_PLL_VAL_10
;
503 pll_100
= AR933X_PLL_VAL_100
;
504 pll_1000
= AR933X_PLL_VAL_1000
;
507 case ATH79_SOC_AR9341
:
508 case ATH79_SOC_AR9342
:
509 case ATH79_SOC_AR9344
:
510 case ATH79_SOC_QCA9558
:
511 pll_10
= AR934X_PLL_VAL_10
;
512 pll_100
= AR934X_PLL_VAL_100
;
513 pll_1000
= AR934X_PLL_VAL_1000
;
520 if (!pll_data
->pll_10
)
521 pll_data
->pll_10
= pll_10
;
523 if (!pll_data
->pll_100
)
524 pll_data
->pll_100
= pll_100
;
526 if (!pll_data
->pll_1000
)
527 pll_data
->pll_1000
= pll_1000
;
530 static int __init
ath79_setup_phy_if_mode(unsigned int id
,
531 struct ag71xx_platform_data
*pdata
)
538 case ATH79_SOC_AR7130
:
539 case ATH79_SOC_AR7141
:
540 case ATH79_SOC_AR7161
:
541 case ATH79_SOC_AR9130
:
542 case ATH79_SOC_AR9132
:
543 switch (pdata
->phy_if_mode
) {
544 case PHY_INTERFACE_MODE_MII
:
545 mii_if
= AR71XX_MII0_CTRL_IF_MII
;
547 case PHY_INTERFACE_MODE_GMII
:
548 mii_if
= AR71XX_MII0_CTRL_IF_GMII
;
550 case PHY_INTERFACE_MODE_RGMII
:
551 mii_if
= AR71XX_MII0_CTRL_IF_RGMII
;
553 case PHY_INTERFACE_MODE_RMII
:
554 mii_if
= AR71XX_MII0_CTRL_IF_RMII
;
559 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL
, mii_if
);
562 case ATH79_SOC_AR7240
:
563 case ATH79_SOC_AR7241
:
564 case ATH79_SOC_AR9330
:
565 case ATH79_SOC_AR9331
:
566 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
569 case ATH79_SOC_AR7242
:
572 case ATH79_SOC_AR9341
:
573 case ATH79_SOC_AR9342
:
574 case ATH79_SOC_AR9344
:
575 case ATH79_SOC_QCA9558
:
576 switch (pdata
->phy_if_mode
) {
577 case PHY_INTERFACE_MODE_MII
:
578 case PHY_INTERFACE_MODE_GMII
:
579 case PHY_INTERFACE_MODE_RGMII
:
580 case PHY_INTERFACE_MODE_RMII
:
593 case ATH79_SOC_AR7130
:
594 case ATH79_SOC_AR7141
:
595 case ATH79_SOC_AR7161
:
596 case ATH79_SOC_AR9130
:
597 case ATH79_SOC_AR9132
:
598 switch (pdata
->phy_if_mode
) {
599 case PHY_INTERFACE_MODE_RMII
:
600 mii_if
= AR71XX_MII1_CTRL_IF_RMII
;
602 case PHY_INTERFACE_MODE_RGMII
:
603 mii_if
= AR71XX_MII1_CTRL_IF_RGMII
;
608 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL
, mii_if
);
611 case ATH79_SOC_AR7240
:
612 case ATH79_SOC_AR7241
:
613 case ATH79_SOC_AR9330
:
614 case ATH79_SOC_AR9331
:
615 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
618 case ATH79_SOC_AR7242
:
621 case ATH79_SOC_AR9341
:
622 case ATH79_SOC_AR9342
:
623 case ATH79_SOC_AR9344
:
624 case ATH79_SOC_QCA9558
:
625 switch (pdata
->phy_if_mode
) {
626 case PHY_INTERFACE_MODE_MII
:
627 case PHY_INTERFACE_MODE_GMII
:
643 void __init
ath79_setup_ar933x_phy4_switch(bool mac
, bool mdio
)
648 base
= ioremap(AR933X_GMAC_BASE
, AR933X_GMAC_SIZE
);
650 t
= __raw_readl(base
+ AR933X_GMAC_REG_ETH_CFG
);
651 t
&= ~(AR933X_ETH_CFG_SW_PHY_SWAP
| AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
);
653 t
|= AR933X_ETH_CFG_SW_PHY_SWAP
;
655 t
|= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
;
656 __raw_writel(t
, base
+ AR933X_GMAC_REG_ETH_CFG
);
661 static int ath79_eth_instance __initdata
;
662 void __init
ath79_register_eth(unsigned int id
)
664 struct platform_device
*pdev
;
665 struct ag71xx_platform_data
*pdata
;
669 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
673 ath79_init_eth_pll_data(id
);
676 pdev
= &ath79_eth0_device
;
678 pdev
= &ath79_eth1_device
;
680 pdata
= pdev
->dev
.platform_data
;
682 err
= ath79_setup_phy_if_mode(id
, pdata
);
685 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
690 case ATH79_SOC_AR7130
:
692 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
693 pdata
->set_speed
= ath79_set_speed_ge0
;
695 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
696 pdata
->set_speed
= ath79_set_speed_ge1
;
700 case ATH79_SOC_AR7141
:
701 case ATH79_SOC_AR7161
:
703 pdata
->ddr_flush
= ath79_ddr_flush_ge0
;
704 pdata
->set_speed
= ath79_set_speed_ge0
;
706 pdata
->ddr_flush
= ath79_ddr_flush_ge1
;
707 pdata
->set_speed
= ath79_set_speed_ge1
;
712 case ATH79_SOC_AR7242
:
714 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
|
715 AR71XX_RESET_GE0_PHY
;
716 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
717 pdata
->set_speed
= ar7242_set_speed_ge0
;
719 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
|
720 AR71XX_RESET_GE1_PHY
;
721 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
722 pdata
->set_speed
= ath79_set_speed_dummy
;
725 pdata
->is_ar724x
= 1;
727 if (!pdata
->fifo_cfg1
)
728 pdata
->fifo_cfg1
= 0x0010ffff;
729 if (!pdata
->fifo_cfg2
)
730 pdata
->fifo_cfg2
= 0x015500aa;
731 if (!pdata
->fifo_cfg3
)
732 pdata
->fifo_cfg3
= 0x01f00140;
735 case ATH79_SOC_AR7241
:
737 pdata
->reset_bit
|= AR724X_RESET_GE0_MDIO
;
739 pdata
->reset_bit
|= AR724X_RESET_GE1_MDIO
;
741 case ATH79_SOC_AR7240
:
743 pdata
->reset_bit
|= AR71XX_RESET_GE0_PHY
;
744 pdata
->ddr_flush
= ar724x_ddr_flush_ge0
;
745 pdata
->set_speed
= ath79_set_speed_dummy
;
747 pdata
->phy_mask
= BIT(4);
749 pdata
->reset_bit
|= AR71XX_RESET_GE1_PHY
;
750 pdata
->ddr_flush
= ar724x_ddr_flush_ge1
;
751 pdata
->set_speed
= ath79_set_speed_dummy
;
753 pdata
->speed
= SPEED_1000
;
754 pdata
->duplex
= DUPLEX_FULL
;
755 pdata
->switch_data
= &ath79_switch_data
;
757 ath79_switch_data
.phy_poll_mask
|= BIT(4);
760 pdata
->is_ar724x
= 1;
761 if (ath79_soc
== ATH79_SOC_AR7240
)
762 pdata
->is_ar7240
= 1;
764 if (!pdata
->fifo_cfg1
)
765 pdata
->fifo_cfg1
= 0x0010ffff;
766 if (!pdata
->fifo_cfg2
)
767 pdata
->fifo_cfg2
= 0x015500aa;
768 if (!pdata
->fifo_cfg3
)
769 pdata
->fifo_cfg3
= 0x01f00140;
772 case ATH79_SOC_AR9130
:
774 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
775 pdata
->set_speed
= ar91xx_set_speed_ge0
;
777 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
778 pdata
->set_speed
= ar91xx_set_speed_ge1
;
780 pdata
->is_ar91xx
= 1;
783 case ATH79_SOC_AR9132
:
785 pdata
->ddr_flush
= ar91xx_ddr_flush_ge0
;
786 pdata
->set_speed
= ar91xx_set_speed_ge0
;
788 pdata
->ddr_flush
= ar91xx_ddr_flush_ge1
;
789 pdata
->set_speed
= ar91xx_set_speed_ge1
;
791 pdata
->is_ar91xx
= 1;
795 case ATH79_SOC_AR9330
:
796 case ATH79_SOC_AR9331
:
798 pdata
->reset_bit
= AR933X_RESET_GE0_MAC
|
799 AR933X_RESET_GE0_MDIO
;
800 pdata
->ddr_flush
= ar933x_ddr_flush_ge0
;
801 pdata
->set_speed
= ath79_set_speed_dummy
;
803 pdata
->phy_mask
= BIT(4);
805 pdata
->reset_bit
= AR933X_RESET_GE1_MAC
|
806 AR933X_RESET_GE1_MDIO
;
807 pdata
->ddr_flush
= ar933x_ddr_flush_ge1
;
808 pdata
->set_speed
= ath79_set_speed_dummy
;
810 pdata
->speed
= SPEED_1000
;
811 pdata
->duplex
= DUPLEX_FULL
;
812 pdata
->switch_data
= &ath79_switch_data
;
814 ath79_switch_data
.phy_poll_mask
|= BIT(4);
818 pdata
->is_ar724x
= 1;
820 if (!pdata
->fifo_cfg1
)
821 pdata
->fifo_cfg1
= 0x0010ffff;
822 if (!pdata
->fifo_cfg2
)
823 pdata
->fifo_cfg2
= 0x015500aa;
824 if (!pdata
->fifo_cfg3
)
825 pdata
->fifo_cfg3
= 0x01f00140;
828 case ATH79_SOC_AR9341
:
829 case ATH79_SOC_AR9342
:
830 case ATH79_SOC_AR9344
:
831 case ATH79_SOC_QCA9558
:
833 pdata
->reset_bit
= AR934X_RESET_GE0_MAC
|
834 AR934X_RESET_GE0_MDIO
;
835 pdata
->set_speed
= ar934x_set_speed_ge0
;
837 pdata
->reset_bit
= AR934X_RESET_GE1_MAC
|
838 AR934X_RESET_GE1_MDIO
;
839 pdata
->set_speed
= ath79_set_speed_dummy
;
841 pdata
->switch_data
= &ath79_switch_data
;
843 /* reset the built-in switch */
844 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH
);
845 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH
);
848 pdata
->ddr_flush
= ath79_ddr_no_flush
;
850 pdata
->is_ar724x
= 1;
852 if (!pdata
->fifo_cfg1
)
853 pdata
->fifo_cfg1
= 0x0010ffff;
854 if (!pdata
->fifo_cfg2
)
855 pdata
->fifo_cfg2
= 0x015500aa;
856 if (!pdata
->fifo_cfg3
)
857 pdata
->fifo_cfg3
= 0x01f00140;
864 switch (pdata
->phy_if_mode
) {
865 case PHY_INTERFACE_MODE_GMII
:
866 case PHY_INTERFACE_MODE_RGMII
:
867 if (!pdata
->has_gbit
) {
868 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
877 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
878 random_ether_addr(pdata
->mac_addr
);
880 "ar71xx: using random MAC address for eth%d\n",
884 if (pdata
->mii_bus_dev
== NULL
) {
886 case ATH79_SOC_AR9341
:
887 case ATH79_SOC_AR9342
:
888 case ATH79_SOC_AR9344
:
889 case ATH79_SOC_QCA9558
:
891 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
893 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
896 case ATH79_SOC_AR7241
:
897 case ATH79_SOC_AR9330
:
898 case ATH79_SOC_AR9331
:
899 pdata
->mii_bus_dev
= &ath79_mdio1_device
.dev
;
903 pdata
->mii_bus_dev
= &ath79_mdio0_device
.dev
;
908 /* Reset the device */
909 ath79_device_reset_set(pdata
->reset_bit
);
912 ath79_device_reset_clear(pdata
->reset_bit
);
915 platform_device_register(pdev
);
916 ath79_eth_instance
++;
919 void __init
ath79_set_mac_base(unsigned char *mac
)
921 memcpy(ath79_mac_base
, mac
, ETH_ALEN
);
924 void __init
ath79_parse_mac_addr(char *mac_str
)
929 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
930 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
933 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
934 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
937 ath79_set_mac_base(tmp
);
939 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
940 "\"%s\"\n", mac_str
);
943 static int __init
ath79_ethaddr_setup(char *str
)
945 ath79_parse_mac_addr(str
);
948 __setup("ethaddr=", ath79_ethaddr_setup
);
950 static int __init
ath79_kmac_setup(char *str
)
952 ath79_parse_mac_addr(str
);
955 __setup("kmac=", ath79_kmac_setup
);
957 void __init
ath79_init_mac(unsigned char *dst
, const unsigned char *src
,
962 if (!is_valid_ether_addr(src
)) {
963 memset(dst
, '\0', ETH_ALEN
);
967 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
973 dst
[3] = (t
>> 16) & 0xff;
974 dst
[4] = (t
>> 8) & 0xff;
978 void __init
ath79_init_local_mac(unsigned char *dst
, const unsigned char *src
)
982 if (!is_valid_ether_addr(src
)) {
983 memset(dst
, '\0', ETH_ALEN
);
987 for (i
= 0; i
< ETH_ALEN
; i
++)