2 * TP-LINK Archer C7 board support
4 * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
6 * Based on the Qualcomm Atheros AP135/AP136 reference board support code
7 * Copyright (c) 2012 Qualcomm Atheros
9 * Permission to use, copy, modify, and/or distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/pci.h>
24 #include <linux/phy.h>
25 #include <linux/gpio.h>
26 #include <linux/platform_device.h>
27 //#include <linux/ath9k_platform.h>
28 #include <linux/ar8216_platform.h>
30 #include <asm/mach-ath79/ar71xx_regs.h>
34 #include "dev-gpio-buttons.h"
35 #include "dev-leds-gpio.h"
36 #include "dev-m25p80.h"
40 #include "machtypes.h"
43 #define ARCHER_C7_GPIO_LED_WLAN2G 12
44 #define ARCHER_C7_GPIO_LED_SYSTEM 14
45 #define ARCHER_C7_GPIO_LED_QSS 15
46 #define ARCHER_C7_GPIO_LED_WLAN5G 17
47 #define ARCHER_C7_GPIO_LED_USB1 18
48 #define ARCHER_C7_GPIO_LED_USB2 19
50 #define ARCHER_C7_GPIO_BTN_RFKILL 13
51 #define ARCHER_C7_GPIO_BTN_RESET 16
53 #define ARCHER_C7_GPIO_USB1_POWER 22
54 #define ARCHER_C7_GPIO_USB2_POWER 21
56 #define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */
57 #define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL)
59 #define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000
61 static const char *archer_c7_part_probes
[] = {
66 static struct flash_platform_data archer_c7_flash_data
= {
67 .part_probes
= archer_c7_part_probes
,
70 static struct gpio_led archer_c7_leds_gpio
[] __initdata
= {
72 .name
= "tp-link:blue:qss",
73 .gpio
= ARCHER_C7_GPIO_LED_QSS
,
77 .name
= "tp-link:blue:system",
78 .gpio
= ARCHER_C7_GPIO_LED_SYSTEM
,
82 .name
= "tp-link:blue:wlan2g",
83 .gpio
= ARCHER_C7_GPIO_LED_WLAN2G
,
87 .name
= "tp-link:blue:wlan5g",
88 .gpio
= ARCHER_C7_GPIO_LED_WLAN5G
,
92 .name
= "tp-link:green:usb1",
93 .gpio
= ARCHER_C7_GPIO_LED_USB1
,
97 .name
= "tp-link:green:usb2",
98 .gpio
= ARCHER_C7_GPIO_LED_USB2
,
103 static struct gpio_keys_button archer_c7_gpio_keys
[] __initdata
= {
105 .desc
= "Reset button",
107 .code
= KEY_WPS_BUTTON
,
108 .debounce_interval
= ARCHER_C7_KEYS_DEBOUNCE_INTERVAL
,
109 .gpio
= ARCHER_C7_GPIO_BTN_RESET
,
113 .desc
= "RFKILL switch",
116 .debounce_interval
= ARCHER_C7_KEYS_DEBOUNCE_INTERVAL
,
117 .gpio
= ARCHER_C7_GPIO_BTN_RFKILL
,
121 /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
122 static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg
= {
123 .mode
= AR8327_PAD_MAC_SGMII
,
124 .sgmii_delay_en
= true,
127 /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
128 static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg
= {
129 .mode
= AR8327_PAD_MAC_RGMII
,
130 .txclk_delay_en
= true,
131 .rxclk_delay_en
= true,
132 .txclk_delay_sel
= AR8327_CLK_DELAY_SEL1
,
133 .rxclk_delay_sel
= AR8327_CLK_DELAY_SEL2
,
136 static struct ar8327_led_cfg archer_c7_ar8327_led_cfg
= {
137 .led_ctrl0
= 0xc737c737,
138 .led_ctrl1
= 0x00000000,
139 .led_ctrl2
= 0x00000000,
140 .led_ctrl3
= 0x0030c300,
144 static struct ar8327_platform_data archer_c7_ar8327_data
= {
145 .pad0_cfg
= &archer_c7_ar8327_pad0_cfg
,
146 .pad6_cfg
= &archer_c7_ar8327_pad6_cfg
,
149 .speed
= AR8327_PORT_SPEED_1000
,
156 .speed
= AR8327_PORT_SPEED_1000
,
161 .led_cfg
= &archer_c7_ar8327_led_cfg
,
164 static struct mdio_board_info archer_c7_mdio0_info
[] = {
166 .bus_id
= "ag71xx-mdio.0",
168 .platform_data
= &archer_c7_ar8327_data
,
172 static void __init
archer_c7_gmac_setup(void)
177 base
= ioremap(QCA955X_GMAC_BASE
, QCA955X_GMAC_SIZE
);
179 t
= __raw_readl(base
+ QCA955X_GMAC_REG_ETH_CFG
);
181 t
&= ~(QCA955X_ETH_CFG_RGMII_EN
| QCA955X_ETH_CFG_GE0_SGMII
);
182 t
|= QCA955X_ETH_CFG_RGMII_EN
;
184 __raw_writel(t
, base
+ QCA955X_GMAC_REG_ETH_CFG
);
189 static void __init
archer_c7_setup(void)
191 u8
*mac
= (u8
*) KSEG1ADDR(0x1f01fc00);
192 u8
*art
= (u8
*) KSEG1ADDR(0x1fff0000);
195 ath79_register_m25p80(&archer_c7_flash_data
);
196 ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio
),
197 archer_c7_leds_gpio
);
198 ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL
,
199 ARRAY_SIZE(archer_c7_gpio_keys
),
200 archer_c7_gpio_keys
);
202 ath79_init_mac(tmpmac
, mac
, -1);
203 ath79_register_wmac(art
+ ARCHER_C7_WMAC_CALDATA_OFFSET
, tmpmac
);
205 ath79_register_pci();
207 mdiobus_register_board_info(archer_c7_mdio0_info
,
208 ARRAY_SIZE(archer_c7_mdio0_info
));
209 ath79_register_mdio(0, 0x0);
211 archer_c7_gmac_setup();
213 /* GMAC0 is connected to the RMGII interface */
214 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_RGMII
;
215 ath79_eth0_data
.phy_mask
= BIT(0);
216 ath79_eth0_data
.mii_bus_dev
= &ath79_mdio0_device
.dev
;
217 ath79_eth0_pll_data
.pll_1000
= 0x56000000;
219 ath79_init_mac(ath79_eth0_data
.mac_addr
, mac
, 1);
220 ath79_register_eth(0);
222 /* GMAC1 is connected to the SGMII interface */
223 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_SGMII
;
224 ath79_eth1_data
.speed
= SPEED_1000
;
225 ath79_eth1_data
.duplex
= DUPLEX_FULL
;
226 ath79_eth1_pll_data
.pll_1000
= 0x03000101;
228 ath79_init_mac(ath79_eth1_data
.mac_addr
, mac
, 0);
229 ath79_register_eth(1);
231 gpio_request_one(ARCHER_C7_GPIO_USB1_POWER
,
232 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
234 gpio_request_one(ARCHER_C7_GPIO_USB2_POWER
,
235 GPIOF_OUT_INIT_HIGH
| GPIOF_EXPORT_DIR_FIXED
,
237 ath79_register_usb();
240 MIPS_MACHINE(ATH79_MACH_ARCHER_C7
, "ARCHER-C7", "TP-LINK Archer C7",