target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c

   1 /*
   2  * TP-LINK Archer C5/C7/TL-WDR4900 v2 board support
   3  *
   4  * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2014 施康成 <tenninjas@tenninjas.ca>
   6  * Copyright (c) 2014 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  * Based on the Qualcomm Atheros AP135/AP136 reference board support code
   9  *   Copyright (c) 2012 Qualcomm Atheros
  10  *
  11  * Permission to use, copy, modify, and/or distribute this software for any
  12  * purpose with or without fee is hereby granted, provided that the above
  13  * copyright notice and this permission notice appear in all copies.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  16  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  18  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  19  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  20  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  21  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/pci.h>
  26 #include <linux/phy.h>
  27 #include <linux/gpio.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/ath9k_platform.h>
  30 #include <linux/ar8216_platform.h>
  31
  32 #include <asm/mach-ath79/ar71xx_regs.h>
  33
  34 #include "common.h"
  35 #include "dev-ap9x-pci.h"
  36 #include "dev-eth.h"
  37 #include "dev-gpio-buttons.h"
  38 #include "dev-leds-gpio.h"
  39 #include "dev-m25p80.h"
  40 #include "dev-spi.h"
  41 #include "dev-usb.h"
  42 #include "dev-wmac.h"
  43 #include "machtypes.h"
  44 #include "pci.h"
  45
  46 #define ARCHER_C7_GPIO_LED_WLAN2G       12
  47 #define ARCHER_C7_GPIO_LED_SYSTEM       14
  48 #define ARCHER_C7_GPIO_LED_QSS          15
  49 #define ARCHER_C7_GPIO_LED_WLAN5G       17
  50 #define ARCHER_C7_GPIO_LED_USB1         18
  51 #define ARCHER_C7_GPIO_LED_USB2         19
  52
  53 #define ARCHER_C7_GPIO_BTN_RFKILL       23
  54 #define ARCHER_C7_V2_GPIO_BTN_RFKILL    23
  55 #define ARCHER_C7_GPIO_BTN_RESET        16
  56
  57 #define ARCHER_C7_GPIO_USB1_POWER       22
  58 #define ARCHER_C7_GPIO_USB2_POWER       21
  59
  60 #define ARCHER_C7_KEYS_POLL_INTERVAL    20      /* msecs */
  61 #define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL)
  62
  63 #define ARCHER_C7_WMAC_CALDATA_OFFSET   0x1000
  64 #define ARCHER_C7_PCIE_CALDATA_OFFSET   0x5000
  65
  66 static const char *archer_c7_part_probes[] = {
  67         "tp-link",
  68         NULL,
  69 };
  70
  71 static struct flash_platform_data archer_c7_flash_data = {
  72         .part_probes    = archer_c7_part_probes,
  73 };
  74
  75 static struct gpio_led archer_c7_leds_gpio[] __initdata = {
  76         {
  77                 .name           = "tp-link:green:qss",
  78                 .gpio           = ARCHER_C7_GPIO_LED_QSS,
  79                 .active_low     = 1,
  80         },
  81         {
  82                 .name           = "tp-link:green:system",
  83                 .gpio           = ARCHER_C7_GPIO_LED_SYSTEM,
  84                 .active_low     = 1,
  85         },
  86         {
  87                 .name           = "tp-link:green:wlan2g",
  88                 .gpio           = ARCHER_C7_GPIO_LED_WLAN2G,
  89                 .active_low     = 1,
  90         },
  91         {
  92                 .name           = "tp-link:green:wlan5g",
  93                 .gpio           = ARCHER_C7_GPIO_LED_WLAN5G,
  94                 .active_low     = 1,
  95         },
  96         {
  97                 .name           = "tp-link:green:usb1",
  98                 .gpio           = ARCHER_C7_GPIO_LED_USB1,
  99                 .active_low     = 1,
 100         },
 101         {
 102                 .name           = "tp-link:green:usb2",
 103                 .gpio           = ARCHER_C7_GPIO_LED_USB2,
 104                 .active_low     = 1,
 105         },
 106 };
 107
 108 static struct gpio_led wdr4900_leds_gpio[] __initdata = {
 109         {
 110                 .name           = "tp-link:blue:qss",
 111                 .gpio           = ARCHER_C7_GPIO_LED_QSS,
 112                 .active_low     = 1,
 113         },
 114         {
 115                 .name           = "tp-link:blue:system",
 116                 .gpio           = ARCHER_C7_GPIO_LED_SYSTEM,
 117                 .active_low     = 1,
 118         },
 119         {
 120                 .name           = "tp-link:blue:wlan2g",
 121                 .gpio           = ARCHER_C7_GPIO_LED_WLAN2G,
 122                 .active_low     = 1,
 123         },
 124         {
 125                 .name           = "tp-link:green:usb1",
 126                 .gpio           = ARCHER_C7_GPIO_LED_USB1,
 127                 .active_low     = 1,
 128         },
 129         {
 130                 .name           = "tp-link:green:usb2",
 131                 .gpio           = ARCHER_C7_GPIO_LED_USB2,
 132                 .active_low     = 1,
 133         },
 134 };
 135
 136 static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = {
 137         {
 138                 .desc           = "Reset button",
 139                 .type           = EV_KEY,
 140                 .code           = KEY_WPS_BUTTON,
 141                 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
 142                 .gpio           = ARCHER_C7_GPIO_BTN_RESET,
 143                 .active_low     = 1,
 144         },
 145         {
 146                 .desc           = "RFKILL switch",
 147                 .type           = EV_SW,
 148                 .code           = KEY_RFKILL,
 149                 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
 150                 .gpio           = ARCHER_C7_GPIO_BTN_RFKILL,
 151         },
 152 };
 153
 154 static struct gpio_keys_button archer_c7_v2_gpio_keys[] __initdata = {
 155         {
 156                 .desc           = "Reset button",
 157                 .type           = EV_KEY,
 158                 .code           = KEY_WPS_BUTTON,
 159                 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
 160                 .gpio           = ARCHER_C7_GPIO_BTN_RESET,
 161                 .active_low     = 1,
 162         },
 163         {
 164                 .desc           = "RFKILL switch",
 165                 .type           = EV_SW,
 166                 .code           = KEY_RFKILL,
 167                 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
 168                 .gpio           = ARCHER_C7_V2_GPIO_BTN_RFKILL,
 169         },
 170 };
 171
 172 static const struct ar8327_led_info archer_c7_leds_ar8327[] = {
 173         AR8327_LED_INFO(PHY0_0, HW, "tp-link:green:wan"),
 174         AR8327_LED_INFO(PHY1_0, HW, "tp-link:green:lan1"),
 175         AR8327_LED_INFO(PHY2_0, HW, "tp-link:green:lan2"),
 176         AR8327_LED_INFO(PHY3_0, HW, "tp-link:green:lan3"),
 177         AR8327_LED_INFO(PHY4_0, HW, "tp-link:green:lan4"),
 178 };
 179
 180 /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
 181 static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = {
 182         .mode = AR8327_PAD_MAC_SGMII,
 183         .sgmii_delay_en = true,
 184 };
 185
 186 /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
 187 static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = {
 188         .mode = AR8327_PAD_MAC_RGMII,
 189         .txclk_delay_en = true,
 190         .rxclk_delay_en = true,
 191         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 192         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 193 };
 194
 195 static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = {
 196         .led_ctrl0 = 0xc737c737,
 197         .led_ctrl1 = 0x00000000,
 198         .led_ctrl2 = 0x00000000,
 199         .led_ctrl3 = 0x0030c300,
 200         .open_drain = false,
 201 };
 202
 203 static struct ar8327_platform_data archer_c7_ar8327_data = {
 204         .pad0_cfg = &archer_c7_ar8327_pad0_cfg,
 205         .pad6_cfg = &archer_c7_ar8327_pad6_cfg,
 206         .port0_cfg = {
 207                 .force_link = 1,
 208                 .speed = AR8327_PORT_SPEED_1000,
 209                 .duplex = 1,
 210                 .txpause = 1,
 211                 .rxpause = 1,
 212         },
 213         .port6_cfg = {
 214                 .force_link = 1,
 215                 .speed = AR8327_PORT_SPEED_1000,
 216                 .duplex = 1,
 217                 .txpause = 1,
 218                 .rxpause = 1,
 219         },
 220         .led_cfg = &archer_c7_ar8327_led_cfg,
 221         .num_leds = ARRAY_SIZE(archer_c7_leds_ar8327),
 222         .leds = archer_c7_leds_ar8327,
 223 };
 224
 225 static struct mdio_board_info archer_c7_mdio0_info[] = {
 226         {
 227                 .bus_id = "ag71xx-mdio.0",
 228                 .mdio_addr = 0,
 229                 .platform_data = &archer_c7_ar8327_data,
 230         },
 231 };
 232
 233 static void __init common_setup(bool pcie_slot)
 234 {
 235         u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
 236         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 237         u8 tmpmac[ETH_ALEN];
 238         u8 tmpmac2[ETH_ALEN];
 239
 240         ath79_register_m25p80(&archer_c7_flash_data);
 241
 242         if (pcie_slot) {
 243                 ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, mac);
 244                 ath79_register_pci();
 245         } else {
 246                 ath79_init_mac(tmpmac, mac, -1);
 247                 ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
 248
 249                 ath79_init_mac(tmpmac2, mac, -2);
 250                 ap9x_pci_setup_wmac_led_pin(0, 0);
 251                 ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac2);
 252         }
 253
 254         mdiobus_register_board_info(archer_c7_mdio0_info,
 255                                     ARRAY_SIZE(archer_c7_mdio0_info));
 256         ath79_register_mdio(0, 0x0);
 257
 258         ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
 259
 260         /* GMAC0 is connected to the RMGII interface */
 261         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 262         ath79_eth0_data.phy_mask = BIT(0);
 263         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 264         ath79_eth0_pll_data.pll_1000 = 0x56000000;
 265
 266         ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
 267         ath79_register_eth(0);
 268
 269         /* GMAC1 is connected to the SGMII interface */
 270         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 271         ath79_eth1_data.speed = SPEED_1000;
 272         ath79_eth1_data.duplex = DUPLEX_FULL;
 273         ath79_eth1_pll_data.pll_1000 = 0x03000101;
 274
 275         ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
 276         ath79_register_eth(1);
 277
 278         gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
 279                          GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
 280                          "USB1 power");
 281         gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
 282                          GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
 283                          "USB2 power");
 284         ath79_register_usb();
 285 }
 286
 287 static void __init archer_c5_setup(void)
 288 {
 289         ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
 290                                         ARRAY_SIZE(archer_c7_gpio_keys),
 291                                         archer_c7_gpio_keys);
 292         ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
 293                                  archer_c7_leds_gpio);
 294         common_setup(true);
 295 }
 296
 297 MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5",
 298              archer_c5_setup);
 299
 300 static void __init archer_c7_setup(void)
 301 {
 302         ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
 303                                         ARRAY_SIZE(archer_c7_gpio_keys),
 304                                         archer_c7_gpio_keys);
 305         ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
 306                                  archer_c7_leds_gpio);
 307         common_setup(true);
 308 }
 309
 310 MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7",
 311              archer_c7_setup);
 312
 313 static void __init archer_c7_v2_setup(void)
 314 {
 315         ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
 316                                         ARRAY_SIZE(archer_c7_v2_gpio_keys),
 317                                         archer_c7_v2_gpio_keys);
 318         ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
 319                                  archer_c7_leds_gpio);
 320         common_setup(true);
 321 }
 322
 323 MIPS_MACHINE(ATH79_MACH_ARCHER_C7_V2, "ARCHER-C7-V2", "TP-LINK Archer C7",
 324              archer_c7_v2_setup);
 325
 326 static void __init tl_wdr4900_v2_setup(void)
 327 {
 328         ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
 329                                         ARRAY_SIZE(archer_c7_gpio_keys),
 330                                         archer_c7_gpio_keys);
 331         ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4900_leds_gpio),
 332                                  wdr4900_leds_gpio);
 333         common_setup(false);
 334 }
 335
 336 MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2",
 337              tl_wdr4900_v2_setup)
 338