2 * MikroTik RouterBOARD 4xx series support
4 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/platform_device.h>
13 #include <linux/irq.h>
14 #include <linux/mdio-gpio.h>
15 #include <linux/mmc/host.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/flash.h>
18 #include <linux/spi/mmc_spi.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
22 #include <asm/mach-ath79/ar71xx_regs.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/rb4xx_cpld.h>
28 #include "dev-gpio-buttons.h"
29 #include "dev-leds-gpio.h"
31 #include "machtypes.h"
34 #define RB4XX_GPIO_USER_LED 4
35 #define RB4XX_GPIO_RESET_SWITCH 7
37 #define RB4XX_GPIO_CPLD_BASE 32
38 #define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
39 #define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
40 #define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
41 #define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
42 #define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
44 #define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */
45 #define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL)
47 static struct gpio_led rb4xx_leds_gpio
[] __initdata
= {
49 .name
= "rb4xx:yellow:user",
50 .gpio
= RB4XX_GPIO_USER_LED
,
53 .name
= "rb4xx:green:led1",
54 .gpio
= RB4XX_GPIO_CPLD_LED1
,
57 .name
= "rb4xx:green:led2",
58 .gpio
= RB4XX_GPIO_CPLD_LED2
,
61 .name
= "rb4xx:green:led3",
62 .gpio
= RB4XX_GPIO_CPLD_LED3
,
65 .name
= "rb4xx:green:led4",
66 .gpio
= RB4XX_GPIO_CPLD_LED4
,
69 .name
= "rb4xx:green:led5",
70 .gpio
= RB4XX_GPIO_CPLD_LED5
,
75 static struct gpio_keys_button rb4xx_gpio_keys
[] __initdata
= {
77 .desc
= "reset_switch",
80 .debounce_interval
= RB4XX_KEYS_DEBOUNCE_INTERVAL
,
81 .gpio
= RB4XX_GPIO_RESET_SWITCH
,
86 static struct platform_device rb4xx_nand_device
= {
91 static struct ath79_pci_irq rb4xx_pci_irqs
[] __initdata
= {
95 .irq
= ATH79_PCI_IRQ(2),
99 .irq
= ATH79_PCI_IRQ(0),
103 .irq
= ATH79_PCI_IRQ(1),
107 .irq
= ATH79_PCI_IRQ(1),
111 .irq
= ATH79_PCI_IRQ(2),
115 .irq
= ATH79_PCI_IRQ(2),
119 .irq
= ATH79_PCI_IRQ(0),
123 .irq
= ATH79_PCI_IRQ(0),
127 .irq
= ATH79_PCI_IRQ(1),
131 .irq
= ATH79_PCI_IRQ(2),
135 .irq
= ATH79_PCI_IRQ(2),
139 .irq
= ATH79_PCI_IRQ(0),
143 static struct mtd_partition rb4xx_partitions
[] = {
145 .name
= "routerboot",
148 .mask_flags
= MTD_WRITEABLE
,
150 .name
= "hard_config",
153 .mask_flags
= MTD_WRITEABLE
,
158 .mask_flags
= MTD_WRITEABLE
,
160 .name
= "soft_config",
166 static struct flash_platform_data rb4xx_flash_data
= {
168 .parts
= rb4xx_partitions
,
169 .nr_parts
= ARRAY_SIZE(rb4xx_partitions
),
172 static struct rb4xx_cpld_platform_data rb4xx_cpld_data
= {
173 .gpio_base
= RB4XX_GPIO_CPLD_BASE
,
176 static struct mmc_spi_platform_data rb4xx_mmc_data
= {
177 .ocr_mask
= MMC_VDD_32_33
| MMC_VDD_33_34
,
180 static struct spi_board_info rb4xx_spi_info
[] = {
184 .max_speed_hz
= 25000000,
185 .modalias
= "m25p80",
186 .platform_data
= &rb4xx_flash_data
,
190 .max_speed_hz
= 25000000,
191 .modalias
= "spi-rb4xx-cpld",
192 .platform_data
= &rb4xx_cpld_data
,
196 static struct spi_board_info rb4xx_microsd_info
[] = {
200 .max_speed_hz
= 25000000,
201 .modalias
= "mmc_spi",
202 .platform_data
= &rb4xx_mmc_data
,
207 static struct resource rb4xx_spi_resources
[] = {
209 .start
= AR71XX_SPI_BASE
,
210 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
211 .flags
= IORESOURCE_MEM
,
215 static struct platform_device rb4xx_spi_device
= {
218 .resource
= rb4xx_spi_resources
,
219 .num_resources
= ARRAY_SIZE(rb4xx_spi_resources
),
222 static void __init
rb4xx_generic_setup(void)
224 ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN
|
225 AR71XX_GPIO_FUNC_SPI_CS2_EN
);
227 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio
),
230 ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL
,
231 ARRAY_SIZE(rb4xx_gpio_keys
),
234 spi_register_board_info(rb4xx_spi_info
, ARRAY_SIZE(rb4xx_spi_info
));
235 platform_device_register(&rb4xx_spi_device
);
236 platform_device_register(&rb4xx_nand_device
);
239 static void __init
rb411_setup(void)
241 rb4xx_generic_setup();
242 spi_register_board_info(rb4xx_microsd_info
,
243 ARRAY_SIZE(rb4xx_microsd_info
));
245 ath79_register_mdio(0, 0xfffffffc);
247 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
248 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_MII
;
249 ath79_eth0_data
.phy_mask
= 0x00000003;
251 ath79_register_eth(0);
253 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs
), rb4xx_pci_irqs
);
254 ath79_register_pci();
257 MIPS_MACHINE(ATH79_MACH_RB_411
, "411", "MikroTik RouterBOARD 411/A/AH",
260 static void __init
rb411u_setup(void)
263 ath79_register_usb();
266 MIPS_MACHINE(ATH79_MACH_RB_411U
, "411U", "MikroTik RouterBOARD 411U",
269 #define RB433_LAN_PHYMASK BIT(0)
270 #define RB433_WAN_PHYMASK BIT(4)
271 #define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
273 static void __init
rb433_setup(void)
275 rb4xx_generic_setup();
276 spi_register_board_info(rb4xx_microsd_info
,
277 ARRAY_SIZE(rb4xx_microsd_info
));
279 ath79_register_mdio(0, ~RB433_MDIO_PHYMASK
);
281 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 1);
282 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_MII
;
283 ath79_eth0_data
.phy_mask
= RB433_LAN_PHYMASK
;
285 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 0);
286 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_RMII
;
287 ath79_eth1_data
.phy_mask
= RB433_WAN_PHYMASK
;
289 ath79_register_eth(1);
290 ath79_register_eth(0);
292 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs
), rb4xx_pci_irqs
);
293 ath79_register_pci();
296 MIPS_MACHINE(ATH79_MACH_RB_433
, "433", "MikroTik RouterBOARD 433/AH",
299 static void __init
rb433u_setup(void)
302 ath79_register_usb();
305 MIPS_MACHINE(ATH79_MACH_RB_433U
, "433U", "MikroTik RouterBOARD 433UAH",
308 #define RB450_LAN_PHYMASK BIT(0)
309 #define RB450_WAN_PHYMASK BIT(4)
310 #define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
312 static void __init
rb450_generic_setup(int gige
)
314 rb4xx_generic_setup();
315 ath79_register_mdio(0, ~RB450_MDIO_PHYMASK
);
317 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 1);
318 ath79_eth0_data
.phy_if_mode
= (gige
) ?
319 PHY_INTERFACE_MODE_RGMII
: PHY_INTERFACE_MODE_MII
;
320 ath79_eth0_data
.phy_mask
= RB450_LAN_PHYMASK
;
322 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 0);
323 ath79_eth1_data
.phy_if_mode
= (gige
) ?
324 PHY_INTERFACE_MODE_RGMII
: PHY_INTERFACE_MODE_RMII
;
325 ath79_eth1_data
.phy_mask
= RB450_WAN_PHYMASK
;
327 ath79_register_eth(1);
328 ath79_register_eth(0);
331 static void __init
rb450_setup(void)
333 rb450_generic_setup(0);
336 MIPS_MACHINE(ATH79_MACH_RB_450
, "450", "MikroTik RouterBOARD 450",
339 static void __init
rb450g_setup(void)
341 rb450_generic_setup(1);
342 spi_register_board_info(rb4xx_microsd_info
,
343 ARRAY_SIZE(rb4xx_microsd_info
));
346 MIPS_MACHINE(ATH79_MACH_RB_450G
, "450G", "MikroTik RouterBOARD 450G",
349 static void __init
rb493_setup(void)
351 rb4xx_generic_setup();
353 ath79_register_mdio(0, 0x3fffff00);
355 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
356 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_MII
;
357 ath79_eth0_data
.speed
= SPEED_100
;
358 ath79_eth0_data
.duplex
= DUPLEX_FULL
;
360 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 1);
361 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_RMII
;
362 ath79_eth1_data
.phy_mask
= 0x00000001;
364 ath79_register_eth(0);
365 ath79_register_eth(1);
367 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs
), rb4xx_pci_irqs
);
368 ath79_register_pci();
371 MIPS_MACHINE(ATH79_MACH_RB_493
, "493", "MikroTik RouterBOARD 493/AH",
374 #define RB493G_GPIO_MDIO_MDC 7
375 #define RB493G_GPIO_MDIO_DATA 8
377 #define RB493G_MDIO_PHYMASK BIT(0)
379 static struct mdio_gpio_platform_data rb493g_mdio_data
= {
380 .mdc
= RB493G_GPIO_MDIO_MDC
,
381 .mdio
= RB493G_GPIO_MDIO_DATA
,
383 .phy_mask
= ~RB493G_MDIO_PHYMASK
,
386 static struct platform_device rb493g_mdio_device
= {
390 .platform_data
= &rb493g_mdio_data
,
394 static void __init
rb493g_setup(void)
396 ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN
|
397 AR71XX_GPIO_FUNC_SPI_CS2_EN
);
399 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio
),
402 spi_register_board_info(rb4xx_spi_info
, ARRAY_SIZE(rb4xx_spi_info
));
403 platform_device_register(&rb4xx_spi_device
);
404 platform_device_register(&rb4xx_nand_device
);
406 ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK
);
408 ath79_init_mac(ath79_eth0_data
.mac_addr
, ath79_mac_base
, 0);
409 ath79_eth0_data
.phy_if_mode
= PHY_INTERFACE_MODE_RGMII
;
410 ath79_eth0_data
.phy_mask
= RB493G_MDIO_PHYMASK
;
411 ath79_eth0_data
.speed
= SPEED_1000
;
412 ath79_eth0_data
.duplex
= DUPLEX_FULL
;
414 ath79_init_mac(ath79_eth1_data
.mac_addr
, ath79_mac_base
, 1);
415 ath79_eth1_data
.phy_if_mode
= PHY_INTERFACE_MODE_RGMII
;
416 ath79_eth1_data
.mii_bus_dev
= &rb493g_mdio_device
.dev
;
417 ath79_eth1_data
.phy_mask
= RB493G_MDIO_PHYMASK
;
418 ath79_eth1_data
.speed
= SPEED_1000
;
419 ath79_eth1_data
.duplex
= DUPLEX_FULL
;
421 platform_device_register(&rb493g_mdio_device
);
423 ath79_register_eth(1);
424 ath79_register_eth(0);
426 ath79_register_usb();
428 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs
), rb4xx_pci_irqs
);
429 ath79_register_pci();
432 MIPS_MACHINE(ATH79_MACH_RB_493G
, "493G", "MikroTik RouterBOARD 493G",