2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_debug
= -1;
28 module_param(ag71xx_debug
, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug
, "Debug level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx
*ag
)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag
, AG71XX_REG_TX_CTRL
),
36 ag71xx_rr(ag
, AG71XX_REG_TX_DESC
),
37 ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag
, AG71XX_REG_RX_CTRL
),
42 ag71xx_rr(ag
, AG71XX_REG_RX_DESC
),
43 ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
));
46 static void ag71xx_dump_regs(struct ag71xx
*ag
)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
51 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
52 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
53 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
54 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
58 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
59 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
63 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
64 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
68 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
69 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
72 static inline void ag71xx_dump_intr(struct ag71xx
*ag
, char *label
, u32 intr
)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag
->dev
->name
, label
, intr
,
76 (intr
& AG71XX_INT_TX_PS
) ? "TXPS " : "",
77 (intr
& AG71XX_INT_TX_UR
) ? "TXUR " : "",
78 (intr
& AG71XX_INT_TX_BE
) ? "TXBE " : "",
79 (intr
& AG71XX_INT_RX_PR
) ? "RXPR " : "",
80 (intr
& AG71XX_INT_RX_OF
) ? "RXOF " : "",
81 (intr
& AG71XX_INT_RX_BE
) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring
*ring
)
89 dma_free_coherent(NULL
, ring
->size
* sizeof(*ring
->descs
),
90 ring
->descs
, ring
->descs_dma
);
93 static int ag71xx_ring_alloc(struct ag71xx_ring
*ring
, unsigned int size
)
97 ring
->descs
= dma_alloc_coherent(NULL
, size
* sizeof(*ring
->descs
),
107 ring
->buf
= kzalloc(size
* sizeof(*ring
->buf
), GFP_KERNEL
);
119 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
121 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
122 struct net_device
*dev
= ag
->dev
;
124 while (ring
->curr
!= ring
->dirty
) {
125 u32 i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
127 if (!ag71xx_desc_empty(&ring
->descs
[i
])) {
128 ring
->descs
[i
].ctrl
= 0;
129 dev
->stats
.tx_errors
++;
132 if (ring
->buf
[i
].skb
)
133 dev_kfree_skb_any(ring
->buf
[i
].skb
);
135 ring
->buf
[i
].skb
= NULL
;
140 /* flush descriptors */
145 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
147 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
150 for (i
= 0; i
< AG71XX_TX_RING_SIZE
; i
++) {
151 ring
->descs
[i
].next
= (u32
) (ring
->descs_dma
+
152 sizeof(*ring
->descs
) * ((i
+ 1) % AG71XX_TX_RING_SIZE
));
154 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
155 ring
->buf
[i
].skb
= NULL
;
158 /* flush descriptors */
165 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
167 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
173 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
174 if (ring
->buf
[i
].skb
)
175 kfree_skb(ring
->buf
[i
].skb
);
179 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
181 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
186 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
187 ring
->descs
[i
].next
= (u32
) (ring
->descs_dma
+
188 sizeof(*ring
->descs
) * ((i
+ 1) % AG71XX_RX_RING_SIZE
));
190 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++) {
193 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
);
199 dma_map_single(NULL
, skb
->data
, AG71XX_RX_PKT_SIZE
,
203 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
205 ring
->buf
[i
].skb
= skb
;
206 ring
->descs
[i
].data
= virt_to_phys(skb
->data
);
207 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
210 /* flush descriptors */
219 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
221 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
225 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
228 i
= ring
->dirty
% AG71XX_RX_RING_SIZE
;
230 if (ring
->buf
[i
].skb
== NULL
) {
233 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
);
237 dma_map_single(NULL
, skb
->data
, AG71XX_RX_PKT_SIZE
,
240 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
243 ring
->buf
[i
].skb
= skb
;
244 ring
->descs
[i
].data
= virt_to_phys(skb
->data
);
247 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
251 /* flush descriptors */
254 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
259 static int ag71xx_rings_init(struct ag71xx
*ag
)
263 ret
= ag71xx_ring_alloc(&ag
->tx_ring
, AG71XX_TX_RING_SIZE
);
267 ag71xx_ring_tx_init(ag
);
269 ret
= ag71xx_ring_alloc(&ag
->rx_ring
, AG71XX_RX_RING_SIZE
);
273 ret
= ag71xx_ring_rx_init(ag
);
277 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
279 ag71xx_ring_rx_clean(ag
);
280 ag71xx_ring_free(&ag
->rx_ring
);
282 ag71xx_ring_tx_clean(ag
);
283 ag71xx_ring_free(&ag
->tx_ring
);
286 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
290 t
= (((u32
) mac
[0]) << 24) | (((u32
) mac
[1]) << 16)
291 | (((u32
) mac
[2]) << 8) | ((u32
) mac
[3]);
293 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
295 t
= (((u32
) mac
[4]) << 24) | (((u32
) mac
[5]) << 16);
296 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
299 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
300 MAC_CFG1_SRX | MAC_CFG1_STX)
301 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
303 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
304 MAC_CFG1_SRX | MAC_CFG1_STX | \
305 MAC_CFG1_TFC | MAC_CFG1_RFC)
306 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
308 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
310 static void ag71xx_dma_reset(struct ag71xx
*ag
)
314 ag71xx_dump_dma_regs(ag
);
317 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
318 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
320 /* clear descriptor addresses */
321 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, 0);
322 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, 0);
324 /* clear pending RX/TX interrupts */
325 for (i
= 0; i
< 256; i
++) {
326 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
327 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
330 /* clear pending errors */
331 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
| RX_STATUS_OF
);
332 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
| TX_STATUS_UR
);
334 if (ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
))
335 printk(KERN_ALERT
"%s: unable to clear DMA Rx status\n",
338 if (ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
))
339 printk(KERN_ALERT
"%s: unable to clear DMA Tx status\n",
342 ag71xx_dump_dma_regs(ag
);
345 static void ag71xx_hw_init(struct ag71xx
*ag
)
347 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
349 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
352 ar71xx_device_stop(pdata
->reset_bit
);
354 ar71xx_device_start(pdata
->reset_bit
);
357 /* setup MAC configuration registers */
358 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
,
359 pdata
->is_ar91xx
? AR91XX_MAC_CFG1_INIT
: AR71XX_MAC_CFG1_INIT
);
360 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
361 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
363 /* setup max frame length */
364 ag71xx_wr(ag
, AG71XX_REG_MAC_MFL
, AG71XX_TX_MTU_LEN
);
366 /* setup MII interface type */
367 ag71xx_mii_ctrl_set_if(ag
, pdata
->mii_if
);
369 /* setup FIFO configuration registers */
370 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, FIFO_CFG0_INIT
);
371 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, 0x0fff0000);
372 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, 0x00001fff);
373 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, 0x0000ffff);
374 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
,
375 pdata
->is_ar91xx
? AR91XX_FIFO_CFG5_INIT
376 : AR71XX_FIFO_CFG5_INIT
);
378 ag71xx_dma_reset(ag
);
381 static void ag71xx_hw_start(struct ag71xx
*ag
)
383 /* start RX engine */
384 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
386 /* enable interrupts */
387 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
390 static void ag71xx_hw_stop(struct ag71xx
*ag
)
392 /* disable all interrupts */
393 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
395 ag71xx_dma_reset(ag
);
398 static int ag71xx_open(struct net_device
*dev
)
400 struct ag71xx
*ag
= netdev_priv(dev
);
403 ret
= ag71xx_rings_init(ag
);
407 napi_enable(&ag
->napi
);
409 netif_carrier_off(dev
);
410 ag71xx_phy_start(ag
);
412 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
413 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
415 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
419 netif_start_queue(dev
);
424 ag71xx_rings_cleanup(ag
);
428 static int ag71xx_stop(struct net_device
*dev
)
430 struct ag71xx
*ag
= netdev_priv(dev
);
433 spin_lock_irqsave(&ag
->lock
, flags
);
435 netif_stop_queue(dev
);
439 netif_carrier_off(dev
);
442 napi_disable(&ag
->napi
);
443 del_timer_sync(&ag
->oom_timer
);
445 spin_unlock_irqrestore(&ag
->lock
, flags
);
447 ag71xx_rings_cleanup(ag
);
452 static int ag71xx_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
454 struct ag71xx
*ag
= netdev_priv(dev
);
455 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
456 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
457 struct ag71xx_desc
*desc
;
461 i
= ring
->curr
% AG71XX_TX_RING_SIZE
;
462 desc
= &ring
->descs
[i
];
464 spin_lock_irqsave(&ag
->lock
, flags
);
466 spin_unlock_irqrestore(&ag
->lock
, flags
);
468 if (!ag71xx_desc_empty(desc
))
472 DBG("%s: packet len is too small\n", ag
->dev
->name
);
476 dma_map_single(NULL
, skb
->data
, skb
->len
, DMA_TO_DEVICE
);
478 ring
->buf
[i
].skb
= skb
;
480 /* setup descriptor fields */
481 desc
->data
= virt_to_phys(skb
->data
);
482 desc
->ctrl
= (skb
->len
& DESC_PKTLEN_M
);
484 /* flush descriptor */
488 if (ring
->curr
== (ring
->dirty
+ AG71XX_TX_THRES_STOP
)) {
489 DBG("%s: tx queue full\n", ag
->dev
->name
);
490 netif_stop_queue(dev
);
493 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
495 /* enable TX engine */
496 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
498 dev
->trans_start
= jiffies
;
503 dev
->stats
.tx_dropped
++;
509 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
511 struct mii_ioctl_data
*data
= (struct mii_ioctl_data
*) &ifr
->ifr_data
;
512 struct ag71xx
*ag
= netdev_priv(dev
);
517 if (ag
->phy_dev
== NULL
)
520 spin_lock_irq(&ag
->lock
);
521 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
522 spin_unlock_irq(&ag
->lock
);
527 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
533 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
540 if (ag
->phy_dev
== NULL
)
543 return phy_mii_ioctl(ag
->phy_dev
, data
, cmd
);
552 static void ag71xx_oom_timer_handler(unsigned long data
)
554 struct net_device
*dev
= (struct net_device
*) data
;
555 struct ag71xx
*ag
= netdev_priv(dev
);
557 netif_rx_schedule(dev
, &ag
->napi
);
560 static void ag71xx_tx_timeout(struct net_device
*dev
)
562 struct ag71xx
*ag
= netdev_priv(dev
);
564 if (netif_msg_tx_err(ag
))
565 printk(KERN_DEBUG
"%s: tx timeout\n", ag
->dev
->name
);
567 schedule_work(&ag
->restart_work
);
570 static void ag71xx_restart_work_func(struct work_struct
*work
)
572 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, restart_work
);
574 ag71xx_stop(ag
->dev
);
575 ag71xx_open(ag
->dev
);
578 static void ag71xx_tx_packets(struct ag71xx
*ag
)
580 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
583 DBG("%s: processing TX ring\n", ag
->dev
->name
);
586 while (ring
->dirty
!= ring
->curr
) {
587 unsigned int i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
588 struct ag71xx_desc
*desc
= &ring
->descs
[i
];
589 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
591 if (!ag71xx_desc_empty(desc
))
594 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
596 ag
->dev
->stats
.tx_bytes
+= skb
->len
;
597 ag
->dev
->stats
.tx_packets
++;
599 dev_kfree_skb_any(skb
);
600 ring
->buf
[i
].skb
= NULL
;
606 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
608 if ((ring
->curr
- ring
->dirty
) < AG71XX_TX_THRES_WAKEUP
)
609 netif_wake_queue(ag
->dev
);
613 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
615 struct net_device
*dev
= ag
->dev
;
616 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
619 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
620 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
622 while (done
< limit
) {
623 unsigned int i
= ring
->curr
% AG71XX_RX_RING_SIZE
;
624 struct ag71xx_desc
*desc
= &ring
->descs
[i
];
628 if (ag71xx_desc_empty(desc
))
631 if ((ring
->dirty
+ AG71XX_RX_RING_SIZE
) == ring
->curr
) {
636 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
638 skb
= ring
->buf
[i
].skb
;
639 pktlen
= ag71xx_desc_pktlen(desc
);
640 pktlen
-= ETH_FCS_LEN
;
642 skb_put(skb
, pktlen
);
645 skb
->protocol
= eth_type_trans(skb
, dev
);
646 skb
->ip_summed
= CHECKSUM_NONE
;
648 netif_receive_skb(skb
);
650 dev
->last_rx
= jiffies
;
651 dev
->stats
.rx_packets
++;
652 dev
->stats
.rx_bytes
+= pktlen
;
654 ring
->buf
[i
].skb
= NULL
;
660 ag71xx_ring_rx_refill(ag
);
662 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
663 dev
->name
, ring
->curr
, ring
->dirty
, done
);
668 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
670 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
671 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
672 struct net_device
*dev
= ag
->dev
;
673 struct ag71xx_ring
*rx_ring
;
679 ag71xx_tx_packets(ag
);
681 DBG("%s: processing RX ring\n", dev
->name
);
682 done
= ag71xx_rx_packets(ag
, limit
);
684 rx_ring
= &ag
->rx_ring
;
685 if (rx_ring
->buf
[rx_ring
->dirty
% AG71XX_RX_RING_SIZE
].skb
== NULL
)
688 status
= ag71xx_rr(ag
, AG71XX_REG_RX_STATUS
);
689 if (unlikely(status
& RX_STATUS_OF
)) {
690 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
691 dev
->stats
.rx_fifo_errors
++;
694 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
698 if (status
& RX_STATUS_PR
)
701 status
= ag71xx_rr(ag
, AG71XX_REG_TX_STATUS
);
702 if (status
& TX_STATUS_PS
)
705 DBG("%s: disable polling mode, done=%d, limit=%d\n",
706 dev
->name
, done
, limit
);
708 netif_rx_complete(dev
, napi
);
710 /* enable interrupts */
711 spin_lock_irqsave(&ag
->lock
, flags
);
712 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
713 spin_unlock_irqrestore(&ag
->lock
, flags
);
718 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
719 dev
->name
, done
, limit
);
723 if (netif_msg_rx_err(ag
))
724 printk(KERN_DEBUG
"%s: out of memory\n", dev
->name
);
726 mod_timer(&ag
->oom_timer
, jiffies
+ AG71XX_OOM_REFILL
);
727 netif_rx_complete(dev
, napi
);
731 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
733 struct net_device
*dev
= dev_id
;
734 struct ag71xx
*ag
= netdev_priv(dev
);
737 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
738 ag71xx_dump_intr(ag
, "raw", status
);
740 if (unlikely(!status
))
743 if (unlikely(status
& AG71XX_INT_ERR
)) {
744 if (status
& AG71XX_INT_TX_BE
) {
745 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
746 dev_err(&dev
->dev
, "TX BUS error\n");
748 if (status
& AG71XX_INT_RX_BE
) {
749 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
750 dev_err(&dev
->dev
, "RX BUS error\n");
754 if (likely(status
& AG71XX_INT_POLL
)) {
755 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
756 DBG("%s: enable polling mode\n", dev
->name
);
757 netif_rx_schedule(dev
, &ag
->napi
);
763 static void ag71xx_set_multicast_list(struct net_device
*dev
)
768 static int __init
ag71xx_probe(struct platform_device
*pdev
)
770 struct net_device
*dev
;
771 struct resource
*res
;
773 struct ag71xx_platform_data
*pdata
;
776 pdata
= pdev
->dev
.platform_data
;
778 dev_err(&pdev
->dev
, "no platform data specified\n");
783 dev
= alloc_etherdev(sizeof(*ag
));
785 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
790 SET_NETDEV_DEV(dev
, &pdev
->dev
);
792 ag
= netdev_priv(dev
);
795 ag
->mii_bus
= &ag71xx_mdio_bus
->mii_bus
;
796 ag
->msg_enable
= netif_msg_init(ag71xx_debug
,
797 AG71XX_DEFAULT_MSG_ENABLE
);
798 spin_lock_init(&ag
->lock
);
800 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base");
802 dev_err(&pdev
->dev
, "no mac_base resource found\n");
807 ag
->mac_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
809 dev_err(&pdev
->dev
, "unable to ioremap mac_base\n");
814 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base2");
816 dev_err(&pdev
->dev
, "no mac_base2 resource found\n");
818 goto err_unmap_base1
;
821 ag
->mac_base2
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
823 dev_err(&pdev
->dev
, "unable to ioremap mac_base2\n");
825 goto err_unmap_base1
;
828 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mii_ctrl");
830 dev_err(&pdev
->dev
, "no mii_ctrl resource found\n");
832 goto err_unmap_base2
;
835 ag
->mii_ctrl
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
837 dev_err(&pdev
->dev
, "unable to ioremap mii_ctrl\n");
839 goto err_unmap_base2
;
842 dev
->irq
= platform_get_irq(pdev
, 0);
843 err
= request_irq(dev
->irq
, ag71xx_interrupt
,
844 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
847 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
848 goto err_unmap_mii_ctrl
;
851 dev
->base_addr
= (unsigned long)ag
->mac_base
;
852 dev
->open
= ag71xx_open
;
853 dev
->stop
= ag71xx_stop
;
854 dev
->hard_start_xmit
= ag71xx_hard_start_xmit
;
855 dev
->set_multicast_list
= ag71xx_set_multicast_list
;
856 dev
->do_ioctl
= ag71xx_do_ioctl
;
857 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
859 dev
->tx_timeout
= ag71xx_tx_timeout
;
860 INIT_WORK(&ag
->restart_work
, ag71xx_restart_work_func
);
862 init_timer(&ag
->oom_timer
);
863 ag
->oom_timer
.data
= (unsigned long) dev
;
864 ag
->oom_timer
.function
= ag71xx_oom_timer_handler
;
866 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
868 if (is_valid_ether_addr(pdata
->mac_addr
))
869 memcpy(dev
->dev_addr
, pdata
->mac_addr
, ETH_ALEN
);
871 dev
->dev_addr
[0] = 0xde;
872 dev
->dev_addr
[1] = 0xad;
873 get_random_bytes(&dev
->dev_addr
[2], 3);
874 dev
->dev_addr
[5] = pdev
->id
& 0xff;
877 err
= register_netdev(dev
);
879 dev_err(&pdev
->dev
, "unable to register net device\n");
883 printk(KERN_INFO
"%s: Atheros AG71xx at 0x%08lx, irq %d\n",
884 dev
->name
, dev
->base_addr
, dev
->irq
);
886 ag71xx_dump_regs(ag
);
890 ag71xx_dump_regs(ag
);
892 /* Reset the mdio bus explicitly */
894 mutex_lock(&ag
->mii_bus
->mdio_lock
);
895 ag
->mii_bus
->reset(ag
->mii_bus
);
896 mutex_unlock(&ag
->mii_bus
->mdio_lock
);
899 err
= ag71xx_phy_connect(ag
);
901 goto err_unregister_netdev
;
903 platform_set_drvdata(pdev
, dev
);
907 err_unregister_netdev
:
908 unregister_netdev(dev
);
910 free_irq(dev
->irq
, dev
);
912 iounmap(ag
->mii_ctrl
);
914 iounmap(ag
->mac_base2
);
916 iounmap(ag
->mac_base
);
920 platform_set_drvdata(pdev
, NULL
);
924 static int __exit
ag71xx_remove(struct platform_device
*pdev
)
926 struct net_device
*dev
= platform_get_drvdata(pdev
);
929 struct ag71xx
*ag
= netdev_priv(dev
);
931 ag71xx_phy_disconnect(ag
);
932 unregister_netdev(dev
);
933 free_irq(dev
->irq
, dev
);
934 iounmap(ag
->mii_ctrl
);
935 iounmap(ag
->mac_base2
);
936 iounmap(ag
->mac_base
);
938 platform_set_drvdata(pdev
, NULL
);
944 static struct platform_driver ag71xx_driver
= {
945 .probe
= ag71xx_probe
,
946 .remove
= __exit_p(ag71xx_remove
),
948 .name
= AG71XX_DRV_NAME
,
952 static int __init
ag71xx_module_init(void)
956 ret
= ag71xx_mdio_driver_init();
960 ret
= platform_driver_register(&ag71xx_driver
);
967 ag71xx_mdio_driver_exit();
972 static void __exit
ag71xx_module_exit(void)
974 platform_driver_unregister(&ag71xx_driver
);
975 ag71xx_mdio_driver_exit();
978 module_init(ag71xx_module_init
);
979 module_exit(ag71xx_module_exit
);
981 MODULE_VERSION(AG71XX_DRV_VERSION
);
982 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
983 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
984 MODULE_LICENSE("GPL v2");
985 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);