2 * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips
3 * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * This driver was base on: net/dsa/mv88e6060.c
6 * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips
7 * Copyright (c) 2008-2009 Marvell Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/version.h>
16 #include <linux/list.h>
17 #include <linux/netdevice.h>
18 #include <linux/phy.h>
22 #define REG_PHY(p) (REG_BASE + (p))
23 #define REG_PORT(p) (REG_BASE + 8 + (p))
24 #define REG_GLOBAL (REG_BASE + 0x0f)
27 static int reg_read(struct dsa_switch
*ds
, int addr
, int reg
)
29 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
30 return mdiobus_read(ds
->master_mii_bus
, addr
, reg
);
32 struct mii_bus
*bus
= dsa_host_dev_to_mii_bus(ds
->master_dev
);
33 return mdiobus_read(bus
, addr
, reg
);
37 #define REG_READ(addr, reg) \
41 __ret = reg_read(ds, addr, reg); \
48 static int reg_write(struct dsa_switch
*ds
, int addr
, int reg
, u16 val
)
50 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
51 return mdiobus_write(ds
->master_mii_bus
, addr
, reg
, val
);
53 struct mii_bus
*bus
= dsa_host_dev_to_mii_bus(ds
->master_dev
);
54 return mdiobus_write(bus
, addr
, reg
, val
);
58 #define REG_WRITE(addr, reg, val) \
62 __ret = reg_write(ds, addr, reg, val); \
67 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
68 static char *mv88e6063_probe(struct mii_bus
*bus
, int sw_addr
)
71 static char *mv88e6063_probe(struct device
*host_dev
, int sw_addr
)
73 struct mii_bus
*bus
= dsa_host_dev_to_mii_bus(host_dev
);
77 ret
= mdiobus_read(bus
, REG_PORT(0), 0x03);
81 return "Marvell 88E6063";
87 static int mv88e6063_switch_reset(struct dsa_switch
*ds
)
93 * Set all ports to the disabled state.
95 for (i
= 0; i
< NUM_PORTS
; i
++) {
96 ret
= REG_READ(REG_PORT(i
), 0x04);
97 REG_WRITE(REG_PORT(i
), 0x04, ret
& 0xfffc);
101 * Wait for transmit queues to drain.
108 REG_WRITE(REG_GLOBAL
, 0x0a, 0xa130);
111 * Wait up to one second for reset to complete.
113 for (i
= 0; i
< 1000; i
++) {
114 ret
= REG_READ(REG_GLOBAL
, 0x00);
115 if ((ret
& 0x8000) == 0x0000)
126 static int mv88e6063_setup_global(struct dsa_switch
*ds
)
129 * Disable discarding of frames with excessive collisions,
130 * set the maximum frame size to 1536 bytes, and mask all
133 REG_WRITE(REG_GLOBAL
, 0x04, 0x0800);
136 * Enable automatic address learning, set the address
137 * database size to 1024 entries, and set the default aging
140 REG_WRITE(REG_GLOBAL
, 0x0a, 0x2130);
145 static int mv88e6063_setup_port(struct dsa_switch
*ds
, int p
)
147 int addr
= REG_PORT(p
);
150 * Do not force flow control, disable Ingress and Egress
151 * Header tagging, disable VLAN tunneling, and set the port
152 * state to Forwarding. Additionally, if this is the CPU
153 * port, enable Ingress and Egress Trailer tagging mode.
155 REG_WRITE(addr
, 0x04, dsa_is_cpu_port(ds
, p
) ? 0x4103 : 0x0003);
158 * Port based VLAN map: give each port its own address
159 * database, allow the CPU port to talk to each of the 'real'
160 * ports, and allow each of the 'real' ports to only talk to
163 REG_WRITE(addr
, 0x06,
165 (dsa_is_cpu_port(ds
, p
) ?
167 (1 << ds
->dst
->cpu_port
)));
170 * Port Association Vector: when learning source addresses
171 * of packets, add the address to the address database using
172 * a port bitmap that has only the bit for this port set and
173 * the other bits clear.
175 REG_WRITE(addr
, 0x0b, 1 << p
);
180 static int mv88e6063_setup(struct dsa_switch
*ds
)
185 ret
= mv88e6063_switch_reset(ds
);
189 /* @@@ initialise atu */
191 ret
= mv88e6063_setup_global(ds
);
195 for (i
= 0; i
< NUM_PORTS
; i
++) {
196 ret
= mv88e6063_setup_port(ds
, i
);
204 static int mv88e6063_set_addr(struct dsa_switch
*ds
, u8
*addr
)
206 REG_WRITE(REG_GLOBAL
, 0x01, (addr
[0] << 8) | addr
[1]);
207 REG_WRITE(REG_GLOBAL
, 0x02, (addr
[2] << 8) | addr
[3]);
208 REG_WRITE(REG_GLOBAL
, 0x03, (addr
[4] << 8) | addr
[5]);
213 static int mv88e6063_port_to_phy_addr(int port
)
215 if (port
>= 0 && port
<= NUM_PORTS
)
216 return REG_PHY(port
);
220 static int mv88e6063_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
224 addr
= mv88e6063_port_to_phy_addr(port
);
228 return reg_read(ds
, addr
, regnum
);
232 mv88e6063_phy_write(struct dsa_switch
*ds
, int port
, int regnum
, u16 val
)
236 addr
= mv88e6063_port_to_phy_addr(port
);
240 return reg_write(ds
, addr
, regnum
, val
);
243 static void mv88e6063_poll_link(struct dsa_switch
*ds
)
247 for (i
= 0; i
< DSA_MAX_PORTS
; i
++) {
248 struct net_device
*dev
;
249 int uninitialized_var(port_status
);
260 if (dev
->flags
& IFF_UP
) {
261 port_status
= reg_read(ds
, REG_PORT(i
), 0x00);
265 link
= !!(port_status
& 0x1000);
269 if (netif_carrier_ok(dev
)) {
270 printk(KERN_INFO
"%s: link down\n", dev
->name
);
271 netif_carrier_off(dev
);
276 speed
= (port_status
& 0x0100) ? 100 : 10;
277 duplex
= (port_status
& 0x0200) ? 1 : 0;
278 fc
= ((port_status
& 0xc000) == 0xc000) ? 1 : 0;
280 if (!netif_carrier_ok(dev
)) {
281 printk(KERN_INFO
"%s: link up, %d Mb/s, %s duplex, "
282 "flow control %sabled\n", dev
->name
,
283 speed
, duplex
? "full" : "half",
285 netif_carrier_on(dev
);
290 static struct dsa_switch_driver mv88e6063_switch_driver
= {
291 .tag_protocol
= htons(ETH_P_TRAILER
),
292 .probe
= mv88e6063_probe
,
293 .setup
= mv88e6063_setup
,
294 .set_addr
= mv88e6063_set_addr
,
295 .phy_read
= mv88e6063_phy_read
,
296 .phy_write
= mv88e6063_phy_write
,
297 .poll_link
= mv88e6063_poll_link
,
300 static int __init
mv88e6063_init(void)
302 register_switch_driver(&mv88e6063_switch_driver
);
305 module_init(mv88e6063_init
);
307 static void __exit
mv88e6063_cleanup(void)
309 unregister_switch_driver(&mv88e6063_switch_driver
);
311 module_exit(mv88e6063_cleanup
);