2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_RESERVED BIT(19)
70 #define AR7240_AT_CTRL_ARP_EN BIT(20)
72 #define AR7240_REG_TAG_PRIORITY 0x70
74 #define AR7240_REG_SERVICE_TAG 0x74
75 #define AR7240_SERVICE_TAG_M BITM(16)
77 #define AR7240_REG_CPU_PORT 0x78
78 #define AR7240_MIRROR_PORT_S 4
79 #define AR7240_CPU_PORT_EN BIT(8)
81 #define AR7240_REG_MIB_FUNCTION0 0x80
82 #define AR7240_MIB_TIMER_M BITM(16)
83 #define AR7240_MIB_AT_HALF_EN BIT(16)
84 #define AR7240_MIB_BUSY BIT(17)
85 #define AR7240_MIB_FUNC_S 24
86 #define AR7240_MIB_FUNC_M BITM(3)
87 #define AR7240_MIB_FUNC_NO_OP 0x0
88 #define AR7240_MIB_FUNC_FLUSH 0x1
89 #define AR7240_MIB_FUNC_CAPTURE 0x3
91 #define AR7240_REG_MDIO_CTRL 0x98
92 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
93 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
94 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
95 #define AR7240_MDIO_CTRL_CMD_WRITE 0
96 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
97 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
98 #define AR7240_MDIO_CTRL_BUSY BIT(31)
100 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
102 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
103 #define AR7240_PORT_STATUS_SPEED_S 0
104 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
105 #define AR7240_PORT_STATUS_SPEED_10 0
106 #define AR7240_PORT_STATUS_SPEED_100 1
107 #define AR7240_PORT_STATUS_SPEED_1000 2
108 #define AR7240_PORT_STATUS_TXMAC BIT(2)
109 #define AR7240_PORT_STATUS_RXMAC BIT(3)
110 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
111 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
112 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
113 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
114 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
115 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
117 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
118 #define AR7240_PORT_CTRL_STATE_M BITM(3)
119 #define AR7240_PORT_CTRL_STATE_DISABLED 0
120 #define AR7240_PORT_CTRL_STATE_BLOCK 1
121 #define AR7240_PORT_CTRL_STATE_LISTEN 2
122 #define AR7240_PORT_CTRL_STATE_LEARN 3
123 #define AR7240_PORT_CTRL_STATE_FORWARD 4
124 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
125 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
126 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
127 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
128 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
129 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
130 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
131 #define AR7240_PORT_CTRL_HEADER BIT(11)
132 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
133 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
134 #define AR7240_PORT_CTRL_LEARN BIT(14)
135 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
136 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
137 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
139 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
141 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
142 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
143 #define AR7240_PORT_VLAN_MODE_S 30
144 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
145 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
146 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
147 #define AR7240_PORT_VLAN_MODE_SECURE 3
150 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
152 #define AR7240_STATS_RXBROAD 0x00
153 #define AR7240_STATS_RXPAUSE 0x04
154 #define AR7240_STATS_RXMULTI 0x08
155 #define AR7240_STATS_RXFCSERR 0x0c
156 #define AR7240_STATS_RXALIGNERR 0x10
157 #define AR7240_STATS_RXRUNT 0x14
158 #define AR7240_STATS_RXFRAGMENT 0x18
159 #define AR7240_STATS_RX64BYTE 0x1c
160 #define AR7240_STATS_RX128BYTE 0x20
161 #define AR7240_STATS_RX256BYTE 0x24
162 #define AR7240_STATS_RX512BYTE 0x28
163 #define AR7240_STATS_RX1024BYTE 0x2c
164 #define AR7240_STATS_RX1518BYTE 0x30
165 #define AR7240_STATS_RXMAXBYTE 0x34
166 #define AR7240_STATS_RXTOOLONG 0x38
167 #define AR7240_STATS_RXGOODBYTE 0x3c
168 #define AR7240_STATS_RXBADBYTE 0x44
169 #define AR7240_STATS_RXOVERFLOW 0x4c
170 #define AR7240_STATS_FILTERED 0x50
171 #define AR7240_STATS_TXBROAD 0x54
172 #define AR7240_STATS_TXPAUSE 0x58
173 #define AR7240_STATS_TXMULTI 0x5c
174 #define AR7240_STATS_TXUNDERRUN 0x60
175 #define AR7240_STATS_TX64BYTE 0x64
176 #define AR7240_STATS_TX128BYTE 0x68
177 #define AR7240_STATS_TX256BYTE 0x6c
178 #define AR7240_STATS_TX512BYTE 0x70
179 #define AR7240_STATS_TX1024BYTE 0x74
180 #define AR7240_STATS_TX1518BYTE 0x78
181 #define AR7240_STATS_TXMAXBYTE 0x7c
182 #define AR7240_STATS_TXOVERSIZE 0x80
183 #define AR7240_STATS_TXBYTE 0x84
184 #define AR7240_STATS_TXCOLLISION 0x8c
185 #define AR7240_STATS_TXABORTCOL 0x90
186 #define AR7240_STATS_TXMULTICOL 0x94
187 #define AR7240_STATS_TXSINGLECOL 0x98
188 #define AR7240_STATS_TXEXCDEFER 0x9c
189 #define AR7240_STATS_TXDEFER 0xa0
190 #define AR7240_STATS_TXLATECOL 0xa4
192 #define AR7240_PORT_CPU 0
193 #define AR7240_NUM_PORTS 6
194 #define AR7240_NUM_PHYS 5
196 #define AR7240_PHY_ID1 0x004d
197 #define AR7240_PHY_ID2 0xd041
199 #define AR934X_PHY_ID1 0x004d
200 #define AR934X_PHY_ID2 0xd042
202 #define AR7240_MAX_VLANS 16
204 #define AR934X_REG_OPER_MODE0 0x04
205 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
206 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
208 #define AR934X_REG_OPER_MODE1 0x08
209 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
211 #define AR934X_REG_FLOOD_MASK 0x2c
212 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
213 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
215 #define AR934X_REG_QM_CTRL 0x3c
216 #define AR934X_QM_CTRL_ARP_EN BIT(15)
218 #define AR934X_REG_AT_CTRL 0x5c
219 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
220 #define AR934X_AT_CTRL_AGE_EN BIT(17)
221 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
223 #define AR934X_MIB_ENABLE BIT(30)
225 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
227 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
228 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
229 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
230 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
231 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
232 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
233 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
234 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
235 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
237 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
238 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
239 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
240 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
241 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
242 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
243 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
245 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
247 struct ar7240sw_port_stat
{
248 unsigned long rx_broadcast
;
249 unsigned long rx_pause
;
250 unsigned long rx_multicast
;
251 unsigned long rx_fcs_error
;
252 unsigned long rx_align_error
;
253 unsigned long rx_runt
;
254 unsigned long rx_fragments
;
255 unsigned long rx_64byte
;
256 unsigned long rx_128byte
;
257 unsigned long rx_256byte
;
258 unsigned long rx_512byte
;
259 unsigned long rx_1024byte
;
260 unsigned long rx_1518byte
;
261 unsigned long rx_maxbyte
;
262 unsigned long rx_toolong
;
263 unsigned long rx_good_byte
;
264 unsigned long rx_bad_byte
;
265 unsigned long rx_overflow
;
266 unsigned long filtered
;
268 unsigned long tx_broadcast
;
269 unsigned long tx_pause
;
270 unsigned long tx_multicast
;
271 unsigned long tx_underrun
;
272 unsigned long tx_64byte
;
273 unsigned long tx_128byte
;
274 unsigned long tx_256byte
;
275 unsigned long tx_512byte
;
276 unsigned long tx_1024byte
;
277 unsigned long tx_1518byte
;
278 unsigned long tx_maxbyte
;
279 unsigned long tx_oversize
;
280 unsigned long tx_byte
;
281 unsigned long tx_collision
;
282 unsigned long tx_abortcol
;
283 unsigned long tx_multicol
;
284 unsigned long tx_singlecol
;
285 unsigned long tx_excdefer
;
286 unsigned long tx_defer
;
287 unsigned long tx_xlatecol
;
291 struct mii_bus
*mii_bus
;
292 struct ag71xx_switch_platform_data
*swdata
;
293 struct switch_dev swdev
;
297 u16 vlan_id
[AR7240_MAX_VLANS
];
298 u8 vlan_table
[AR7240_MAX_VLANS
];
300 u16 pvid
[AR7240_NUM_PORTS
];
304 struct ar7240sw_port_stat port_stats
[AR7240_NUM_PORTS
];
307 struct ar7240sw_hw_stat
{
308 char string
[ETH_GSTRING_LEN
];
313 static DEFINE_MUTEX(reg_mutex
);
315 static inline int sw_is_ar7240(struct ar7240sw
*as
)
317 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR7240
;
320 static inline int sw_is_ar934x(struct ar7240sw
*as
)
322 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR934X
;
325 static inline u32
ar7240sw_port_mask(struct ar7240sw
*as
, int port
)
330 static inline u32
ar7240sw_port_mask_all(struct ar7240sw
*as
)
332 return BIT(as
->swdev
.ports
) - 1;
335 static inline u32
ar7240sw_port_mask_but(struct ar7240sw
*as
, int port
)
337 return ar7240sw_port_mask_all(as
) & ~BIT(port
);
340 static inline u16
mk_phy_addr(u32 reg
)
342 return 0x17 & ((reg
>> 4) | 0x10);
345 static inline u16
mk_phy_reg(u32 reg
)
347 return (reg
<< 1) & 0x1e;
350 static inline u16
mk_high_addr(u32 reg
)
352 return (reg
>> 7) & 0x1ff;
355 static u32
__ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg
)
362 reg
= (reg
& 0xfffffffc) >> 2;
363 phy_addr
= mk_phy_addr(reg
);
364 phy_reg
= mk_phy_reg(reg
);
366 local_irq_save(flags
);
367 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
368 lo
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
);
369 hi
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
+ 1);
370 local_irq_restore(flags
);
372 return (hi
<< 16) | lo
;
375 static void __ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg
, u32 val
)
381 reg
= (reg
& 0xfffffffc) >> 2;
382 phy_addr
= mk_phy_addr(reg
);
383 phy_reg
= mk_phy_reg(reg
);
385 local_irq_save(flags
);
386 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
387 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
+ 1, (val
>> 16));
388 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
, (val
& 0xffff));
389 local_irq_restore(flags
);
392 static u32
ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg_addr
)
396 mutex_lock(®_mutex
);
397 ret
= __ar7240sw_reg_read(mii
, reg_addr
);
398 mutex_unlock(®_mutex
);
403 static void ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg_addr
, u32 reg_val
)
405 mutex_lock(®_mutex
);
406 __ar7240sw_reg_write(mii
, reg_addr
, reg_val
);
407 mutex_unlock(®_mutex
);
410 static u32
ar7240sw_reg_rmw(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
)
414 mutex_lock(®_mutex
);
415 t
= __ar7240sw_reg_read(mii
, reg
);
418 __ar7240sw_reg_write(mii
, reg
, t
);
419 mutex_unlock(®_mutex
);
424 static void ar7240sw_reg_set(struct mii_bus
*mii
, u32 reg
, u32 val
)
428 mutex_lock(®_mutex
);
429 t
= __ar7240sw_reg_read(mii
, reg
);
431 __ar7240sw_reg_write(mii
, reg
, t
);
432 mutex_unlock(®_mutex
);
435 static int __ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
440 for (i
= 0; i
< timeout
; i
++) {
443 t
= __ar7240sw_reg_read(mii
, reg
);
444 if ((t
& mask
) == val
)
453 static int ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
458 mutex_lock(®_mutex
);
459 ret
= __ar7240sw_reg_wait(mii
, reg
, mask
, val
, timeout
);
460 mutex_unlock(®_mutex
);
464 u16
ar7240sw_phy_read(struct mii_bus
*mii
, unsigned phy_addr
,
470 if (phy_addr
>= AR7240_NUM_PHYS
)
473 mutex_lock(®_mutex
);
474 t
= (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
475 (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
476 AR7240_MDIO_CTRL_MASTER_EN
|
477 AR7240_MDIO_CTRL_BUSY
|
478 AR7240_MDIO_CTRL_CMD_READ
;
480 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
481 err
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
482 AR7240_MDIO_CTRL_BUSY
, 0, 5);
484 val
= __ar7240sw_reg_read(mii
, AR7240_REG_MDIO_CTRL
);
485 mutex_unlock(®_mutex
);
487 return val
& AR7240_MDIO_CTRL_DATA_M
;
490 int ar7240sw_phy_write(struct mii_bus
*mii
, unsigned phy_addr
,
491 unsigned reg_addr
, u16 reg_val
)
496 if (phy_addr
>= AR7240_NUM_PHYS
)
499 mutex_lock(®_mutex
);
500 t
= (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
501 (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
502 AR7240_MDIO_CTRL_MASTER_EN
|
503 AR7240_MDIO_CTRL_BUSY
|
504 AR7240_MDIO_CTRL_CMD_WRITE
|
507 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
508 ret
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
509 AR7240_MDIO_CTRL_BUSY
, 0, 5);
510 mutex_unlock(®_mutex
);
515 static int ar7240sw_capture_stats(struct ar7240sw
*as
)
517 struct mii_bus
*mii
= as
->mii_bus
;
521 write_lock(&as
->stats_lock
);
523 /* Capture the hardware statistics for all ports */
524 ar7240sw_reg_rmw(mii
, AR7240_REG_MIB_FUNCTION0
,
525 (AR7240_MIB_FUNC_M
<< AR7240_MIB_FUNC_S
),
526 (AR7240_MIB_FUNC_CAPTURE
<< AR7240_MIB_FUNC_S
));
528 /* Wait for the capturing to complete. */
529 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MIB_FUNCTION0
,
530 AR7240_MIB_BUSY
, 0, 10);
535 for (port
= 0; port
< AR7240_NUM_PORTS
; port
++) {
537 struct ar7240sw_port_stat
*stats
;
539 base
= AR7240_REG_STATS_BASE(port
);
540 stats
= &as
->port_stats
[port
];
542 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
544 stats
->rx_good_byte
+= READ_STAT(RXGOODBYTE
);
545 stats
->tx_byte
+= READ_STAT(TXBYTE
);
553 write_unlock(&as
->stats_lock
);
557 static void ar7240sw_disable_port(struct ar7240sw
*as
, unsigned port
)
559 ar7240sw_reg_write(as
->mii_bus
, AR7240_REG_PORT_CTRL(port
),
560 AR7240_PORT_CTRL_STATE_DISABLED
);
563 static void ar7240sw_setup(struct ar7240sw
*as
)
565 struct mii_bus
*mii
= as
->mii_bus
;
567 /* Enable CPU port, and disable mirror port */
568 ar7240sw_reg_write(mii
, AR7240_REG_CPU_PORT
,
570 (15 << AR7240_MIRROR_PORT_S
));
572 /* Setup TAG priority mapping */
573 ar7240sw_reg_write(mii
, AR7240_REG_TAG_PRIORITY
, 0xfa50);
575 if (sw_is_ar934x(as
)) {
576 /* Enable aging, MAC replacing */
577 ar7240sw_reg_write(mii
, AR934X_REG_AT_CTRL
,
578 0x2b /* 5 min age time */ |
579 AR934X_AT_CTRL_AGE_EN
|
580 AR934X_AT_CTRL_LEARN_CHANGE
);
581 /* Enable ARP frame acknowledge */
582 ar7240sw_reg_set(mii
, AR934X_REG_QM_CTRL
,
583 AR934X_QM_CTRL_ARP_EN
);
584 /* Enable Broadcast/Multicast frames transmitted to the CPU */
585 ar7240sw_reg_set(mii
, AR934X_REG_FLOOD_MASK
,
586 AR934X_FLOOD_MASK_BC_DP(0) |
587 AR934X_FLOOD_MASK_MC_DP(0));
589 /* Enable MIB counters */
590 ar7240sw_reg_set(mii
, AR7240_REG_MIB_FUNCTION0
,
594 /* Enable ARP frame acknowledge, aging, MAC replacing */
595 ar7240sw_reg_write(mii
, AR7240_REG_AT_CTRL
,
596 AR7240_AT_CTRL_RESERVED
|
597 0x2b /* 5 min age time */ |
598 AR7240_AT_CTRL_AGE_EN
|
599 AR7240_AT_CTRL_ARP_EN
|
600 AR7240_AT_CTRL_LEARN_CHANGE
);
601 /* Enable Broadcast frames transmitted to the CPU */
602 ar7240sw_reg_set(mii
, AR7240_REG_FLOOD_MASK
,
603 AR7240_FLOOD_MASK_BROAD_TO_CPU
);
607 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
, AR7240_GLOBAL_CTRL_MTU_M
,
610 /* setup Service TAG */
611 ar7240sw_reg_rmw(mii
, AR7240_REG_SERVICE_TAG
, AR7240_SERVICE_TAG_M
, 0);
614 static int ar7240sw_reset(struct ar7240sw
*as
)
616 struct mii_bus
*mii
= as
->mii_bus
;
620 /* Set all ports to disabled state. */
621 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
622 ar7240sw_disable_port(as
, i
);
624 /* Wait for transmit queues to drain. */
627 /* Reset the switch. */
628 ar7240sw_reg_write(mii
, AR7240_REG_MASK_CTRL
,
629 AR7240_MASK_CTRL_SOFT_RESET
);
631 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MASK_CTRL
,
632 AR7240_MASK_CTRL_SOFT_RESET
, 0, 1000);
635 for (i
= 0; i
< AR7240_NUM_PHYS
; i
++) {
636 ar7240sw_phy_write(mii
, i
, MII_ADVERTISE
,
637 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
638 ADVERTISE_PAUSE_ASYM
);
639 ar7240sw_phy_write(mii
, i
, MII_BMCR
,
640 BMCR_RESET
| BMCR_ANENABLE
);
648 static void ar7240sw_setup_port(struct ar7240sw
*as
, unsigned port
, u8 portmask
)
650 struct mii_bus
*mii
= as
->mii_bus
;
654 ctrl
= AR7240_PORT_CTRL_STATE_FORWARD
| AR7240_PORT_CTRL_LEARN
|
655 AR7240_PORT_CTRL_SINGLE_VLAN
;
657 if (port
== AR7240_PORT_CPU
) {
658 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
659 AR7240_PORT_STATUS_SPEED_1000
|
660 AR7240_PORT_STATUS_TXFLOW
|
661 AR7240_PORT_STATUS_RXFLOW
|
662 AR7240_PORT_STATUS_TXMAC
|
663 AR7240_PORT_STATUS_RXMAC
|
664 AR7240_PORT_STATUS_DUPLEX
);
666 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
667 AR7240_PORT_STATUS_LINK_AUTO
);
670 /* Set the default VID for this port */
672 vid
= as
->vlan_id
[as
->pvid
[port
]];
673 mode
= AR7240_PORT_VLAN_MODE_SECURE
;
676 mode
= AR7240_PORT_VLAN_MODE_PORT_ONLY
;
680 if (as
->vlan_tagged
& BIT(port
))
681 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_ADD
<<
682 AR7240_PORT_CTRL_VLAN_MODE_S
;
684 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_STRIP
<<
685 AR7240_PORT_CTRL_VLAN_MODE_S
;
687 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_KEEP
<<
688 AR7240_PORT_CTRL_VLAN_MODE_S
;
692 if (port
== AR7240_PORT_CPU
)
693 portmask
= ar7240sw_port_mask_but(as
, AR7240_PORT_CPU
);
695 portmask
= ar7240sw_port_mask(as
, AR7240_PORT_CPU
);
698 /* allow the port to talk to all other ports, but exclude its
699 * own ID to prevent frames from being reflected back to the
700 * port that they came from */
701 portmask
&= ar7240sw_port_mask_but(as
, port
);
703 ar7240sw_reg_write(mii
, AR7240_REG_PORT_CTRL(port
), ctrl
);
704 if (sw_is_ar934x(as
)) {
707 vlan1
= (vid
<< AR934X_PORT_VLAN1_DEFAULT_CVID_S
);
708 vlan2
= (portmask
<< AR934X_PORT_VLAN2_PORT_VID_MEM_S
) |
709 (mode
<< AR934X_PORT_VLAN2_8021Q_MODE_S
);
710 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN1(port
), vlan1
);
711 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN2(port
), vlan2
);
715 vlan
= vid
| (mode
<< AR7240_PORT_VLAN_MODE_S
) |
716 (portmask
<< AR7240_PORT_VLAN_DEST_PORTS_S
);
718 ar7240sw_reg_write(mii
, AR7240_REG_PORT_VLAN(port
), vlan
);
722 static int ar7240_set_addr(struct ar7240sw
*as
, u8
*addr
)
724 struct mii_bus
*mii
= as
->mii_bus
;
727 t
= (addr
[4] << 8) | addr
[5];
728 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR0
, t
);
730 t
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
731 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR1
, t
);
737 ar7240_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
738 struct switch_val
*val
)
740 struct ar7240sw
*as
= sw_to_ar7240(dev
);
741 as
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
746 ar7240_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
747 struct switch_val
*val
)
749 struct ar7240sw
*as
= sw_to_ar7240(dev
);
750 val
->value
.i
= as
->vlan_id
[val
->port_vlan
];
755 ar7240_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
757 struct ar7240sw
*as
= sw_to_ar7240(dev
);
759 /* make sure no invalid PVIDs get set */
761 if (vlan
>= dev
->vlans
)
764 as
->pvid
[port
] = vlan
;
769 ar7240_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
771 struct ar7240sw
*as
= sw_to_ar7240(dev
);
772 *vlan
= as
->pvid
[port
];
777 ar7240_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
779 struct ar7240sw
*as
= sw_to_ar7240(dev
);
780 u8 ports
= as
->vlan_table
[val
->port_vlan
];
784 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
785 struct switch_port
*p
;
787 if (!(ports
& (1 << i
)))
790 p
= &val
->value
.ports
[val
->len
++];
792 if (as
->vlan_tagged
& (1 << i
))
793 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
801 ar7240_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
803 struct ar7240sw
*as
= sw_to_ar7240(dev
);
804 u8
*vt
= &as
->vlan_table
[val
->port_vlan
];
808 for (i
= 0; i
< val
->len
; i
++) {
809 struct switch_port
*p
= &val
->value
.ports
[i
];
811 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
812 as
->vlan_tagged
|= (1 << p
->id
);
814 as
->vlan_tagged
&= ~(1 << p
->id
);
815 as
->pvid
[p
->id
] = val
->port_vlan
;
817 /* make sure that an untagged port does not
818 * appear in other vlans */
819 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
820 if (j
== val
->port_vlan
)
822 as
->vlan_table
[j
] &= ~(1 << p
->id
);
832 ar7240_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
833 struct switch_val
*val
)
835 struct ar7240sw
*as
= sw_to_ar7240(dev
);
836 as
->vlan
= !!val
->value
.i
;
841 ar7240_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
842 struct switch_val
*val
)
844 struct ar7240sw
*as
= sw_to_ar7240(dev
);
845 val
->value
.i
= as
->vlan
;
850 ar7240_vtu_op(struct ar7240sw
*as
, u32 op
, u32 val
)
852 struct mii_bus
*mii
= as
->mii_bus
;
854 if (ar7240sw_reg_wait(mii
, AR7240_REG_VTU
, AR7240_VTU_ACTIVE
, 0, 5))
857 if ((op
& AR7240_VTU_OP
) == AR7240_VTU_OP_LOAD
) {
858 val
&= AR7240_VTUDATA_MEMBER
;
859 val
|= AR7240_VTUDATA_VALID
;
860 ar7240sw_reg_write(mii
, AR7240_REG_VTU_DATA
, val
);
862 op
|= AR7240_VTU_ACTIVE
;
863 ar7240sw_reg_write(mii
, AR7240_REG_VTU
, op
);
867 ar7240_hw_apply(struct switch_dev
*dev
)
869 struct ar7240sw
*as
= sw_to_ar7240(dev
);
870 u8 portmask
[AR7240_NUM_PORTS
];
873 /* flush all vlan translation unit entries */
874 ar7240_vtu_op(as
, AR7240_VTU_OP_FLUSH
, 0);
876 memset(portmask
, 0, sizeof(portmask
));
878 /* calculate the port destination masks and load vlans
879 * into the vlan translation unit */
880 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
881 u8 vp
= as
->vlan_table
[j
];
886 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
889 portmask
[i
] |= vp
& ~mask
;
894 (as
->vlan_id
[j
] << AR7240_VTU_VID_S
),
899 * isolate all ports, but connect them to the cpu port */
900 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
901 if (i
== AR7240_PORT_CPU
)
904 portmask
[i
] = 1 << AR7240_PORT_CPU
;
905 portmask
[AR7240_PORT_CPU
] |= (1 << i
);
909 /* update the port destination mask registers and tag settings */
910 for (i
= 0; i
< as
->swdev
.ports
; i
++)
911 ar7240sw_setup_port(as
, i
, portmask
[i
]);
917 ar7240_reset_switch(struct switch_dev
*dev
)
919 struct ar7240sw
*as
= sw_to_ar7240(dev
);
925 ar7240_get_port_link(struct switch_dev
*dev
, int port
,
926 struct switch_port_link
*link
)
928 struct ar7240sw
*as
= sw_to_ar7240(dev
);
929 struct mii_bus
*mii
= as
->mii_bus
;
932 if (port
> AR7240_NUM_PORTS
)
935 status
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_STATUS(port
));
936 link
->aneg
= !!(status
& AR7240_PORT_STATUS_LINK_AUTO
);
938 link
->link
= !!(status
& AR7240_PORT_STATUS_LINK_UP
);
945 link
->duplex
= !!(status
& AR7240_PORT_STATUS_DUPLEX
);
946 link
->tx_flow
= !!(status
& AR7240_PORT_STATUS_TXFLOW
);
947 link
->rx_flow
= !!(status
& AR7240_PORT_STATUS_RXFLOW
);
948 switch (status
& AR7240_PORT_STATUS_SPEED_M
) {
949 case AR7240_PORT_STATUS_SPEED_10
:
950 link
->speed
= SWITCH_PORT_SPEED_10
;
952 case AR7240_PORT_STATUS_SPEED_100
:
953 link
->speed
= SWITCH_PORT_SPEED_100
;
955 case AR7240_PORT_STATUS_SPEED_1000
:
956 link
->speed
= SWITCH_PORT_SPEED_1000
;
964 ar7240_get_port_stats(struct switch_dev
*dev
, int port
,
965 struct switch_port_stats
*stats
)
967 struct ar7240sw
*as
= sw_to_ar7240(dev
);
969 if (port
> AR7240_NUM_PORTS
)
972 ar7240sw_capture_stats(as
);
974 read_lock(&as
->stats_lock
);
975 stats
->rx_bytes
= as
->port_stats
[port
].rx_good_byte
;
976 stats
->tx_bytes
= as
->port_stats
[port
].tx_byte
;
977 read_unlock(&as
->stats_lock
);
982 static struct switch_attr ar7240_globals
[] = {
984 .type
= SWITCH_TYPE_INT
,
985 .name
= "enable_vlan",
986 .description
= "Enable VLAN mode",
987 .set
= ar7240_set_vlan
,
988 .get
= ar7240_get_vlan
,
993 static struct switch_attr ar7240_port
[] = {
996 static struct switch_attr ar7240_vlan
[] = {
998 .type
= SWITCH_TYPE_INT
,
1000 .description
= "VLAN ID",
1001 .set
= ar7240_set_vid
,
1002 .get
= ar7240_get_vid
,
1007 static const struct switch_dev_ops ar7240_ops
= {
1009 .attr
= ar7240_globals
,
1010 .n_attr
= ARRAY_SIZE(ar7240_globals
),
1013 .attr
= ar7240_port
,
1014 .n_attr
= ARRAY_SIZE(ar7240_port
),
1017 .attr
= ar7240_vlan
,
1018 .n_attr
= ARRAY_SIZE(ar7240_vlan
),
1020 .get_port_pvid
= ar7240_get_pvid
,
1021 .set_port_pvid
= ar7240_set_pvid
,
1022 .get_vlan_ports
= ar7240_get_ports
,
1023 .set_vlan_ports
= ar7240_set_ports
,
1024 .apply_config
= ar7240_hw_apply
,
1025 .reset_switch
= ar7240_reset_switch
,
1026 .get_port_link
= ar7240_get_port_link
,
1027 .get_port_stats
= ar7240_get_port_stats
,
1030 static struct ar7240sw
*ar7240_probe(struct ag71xx
*ag
)
1032 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
1033 struct mii_bus
*mii
= ag
->mii_bus
;
1034 struct ar7240sw
*as
;
1035 struct switch_dev
*swdev
;
1041 phy_id1
= ar7240sw_phy_read(mii
, 0, MII_PHYSID1
);
1042 phy_id2
= ar7240sw_phy_read(mii
, 0, MII_PHYSID2
);
1043 if ((phy_id1
!= AR7240_PHY_ID1
|| phy_id2
!= AR7240_PHY_ID2
) &&
1044 (phy_id1
!= AR934X_PHY_ID1
|| phy_id2
!= AR934X_PHY_ID2
)) {
1045 pr_err("%s: unknown phy id '%04x:%04x'\n",
1046 dev_name(&mii
->dev
), phy_id1
, phy_id2
);
1050 as
= kzalloc(sizeof(*as
), GFP_KERNEL
);
1055 as
->swdata
= pdata
->switch_data
;
1059 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_MASK_CTRL
);
1060 as
->ver
= (ctrl
>> AR7240_MASK_CTRL_VERSION_S
) &
1061 AR7240_MASK_CTRL_VERSION_M
;
1063 if (sw_is_ar7240(as
)) {
1064 swdev
->name
= "AR7240/AR9330 built-in switch";
1065 swdev
->ports
= AR7240_NUM_PORTS
- 1;
1066 } else if (sw_is_ar934x(as
)) {
1067 swdev
->name
= "AR934X built-in switch";
1069 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
1070 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
1071 AR934X_OPER_MODE0_MAC_GMII_EN
);
1072 } else if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
1073 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
1074 AR934X_OPER_MODE0_PHY_MII_EN
);
1076 pr_err("%s: invalid PHY interface mode\n",
1077 dev_name(&mii
->dev
));
1081 if (as
->swdata
->phy4_mii_en
) {
1082 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE1
,
1083 AR934X_REG_OPER_MODE1_PHY4_MII_EN
);
1084 swdev
->ports
= AR7240_NUM_PORTS
- 1;
1086 swdev
->ports
= AR7240_NUM_PORTS
;
1089 pr_err("%s: unsupported chip, ctrl=%08x\n",
1090 dev_name(&mii
->dev
), ctrl
);
1094 swdev
->cpu_port
= AR7240_PORT_CPU
;
1095 swdev
->vlans
= AR7240_MAX_VLANS
;
1096 swdev
->ops
= &ar7240_ops
;
1098 if (register_switch(&as
->swdev
, ag
->dev
) < 0)
1101 pr_info("%s: Found an %s\n", dev_name(&mii
->dev
), swdev
->name
);
1103 /* initialize defaults */
1104 for (i
= 0; i
< AR7240_MAX_VLANS
; i
++)
1107 as
->vlan_table
[0] = ar7240sw_port_mask_all(as
);
1116 static void link_function(struct work_struct
*work
) {
1117 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, link_work
.work
);
1118 struct ar7240sw
*as
= ag
->phy_priv
;
1119 unsigned long flags
;
1124 mask
= ~as
->swdata
->phy_poll_mask
;
1125 for (i
= 0; i
< AR7240_NUM_PHYS
; i
++) {
1128 if (!(mask
& BIT(i
)))
1131 link
= ar7240sw_phy_read(ag
->mii_bus
, i
, MII_BMSR
);
1132 if (link
& BMSR_LSTATUS
) {
1138 spin_lock_irqsave(&ag
->lock
, flags
);
1139 if (status
!= ag
->link
) {
1141 ag71xx_link_adjust(ag
);
1143 spin_unlock_irqrestore(&ag
->lock
, flags
);
1145 schedule_delayed_work(&ag
->link_work
, HZ
/ 2);
1148 void ag71xx_ar7240_start(struct ag71xx
*ag
)
1150 struct ar7240sw
*as
= ag
->phy_priv
;
1154 ag
->speed
= SPEED_1000
;
1157 ar7240_set_addr(as
, ag
->dev
->dev_addr
);
1158 ar7240_hw_apply(&as
->swdev
);
1160 schedule_delayed_work(&ag
->link_work
, HZ
/ 10);
1163 void ag71xx_ar7240_stop(struct ag71xx
*ag
)
1165 cancel_delayed_work_sync(&ag
->link_work
);
1168 int ag71xx_ar7240_init(struct ag71xx
*ag
)
1170 struct ar7240sw
*as
;
1172 as
= ar7240_probe(ag
);
1179 rwlock_init(&as
->stats_lock
);
1180 INIT_DELAYED_WORK(&ag
->link_work
, link_function
);
1185 void ag71xx_ar7240_cleanup(struct ag71xx
*ag
)
1187 struct ar7240sw
*as
= ag
->phy_priv
;
1192 unregister_switch(&as
->swdev
);
1194 ag
->phy_priv
= NULL
;