target/linux/ar71xx/patches-3.8/021-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch

   1 From 0f0f7d810226c734141a20de85289dbb0dda8f96 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Thu, 7 Feb 2013 19:28:14 +0000
   4 Subject: [PATCH] MIPS: pci-ar71xx: use dynamically allocated PCI controller
   5  structure
   6
   7 commit f18118a868f1f7e7bdfea176a204fcc44fae2985 upstream.
   8
   9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  10 Patchwork: http://patchwork.linux-mips.org/patch/4926/
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 ---
  13  arch/mips/pci/pci-ar71xx.c |   84 ++++++++++++++++++++++++++++----------------
  14  1 file changed, 53 insertions(+), 31 deletions(-)
  15
  16 --- a/arch/mips/pci/pci-ar71xx.c
  17 +++ b/arch/mips/pci/pci-ar71xx.c
  18 @@ -48,8 +48,12 @@
  19
  20  #define AR71XX_PCI_IRQ_COUNT           5
  21
  22 -static DEFINE_SPINLOCK(ar71xx_pci_lock);
  23 -static void __iomem *ar71xx_pcicfg_base;
  24 +struct ar71xx_pci_controller {
  25 +       void __iomem *cfg_base;
  26 +       spinlock_t lock;
  27 +       int irq;
  28 +       struct pci_controller pci_ctrl;
  29 +};
  30
  31  /* Byte lane enable bits */
  32  static const u8 ar71xx_pci_ble_table[4][4] = {
  33 @@ -92,9 +96,18 @@ static inline u32 ar71xx_pci_bus_addr(st
  34         return ret;
  35  }
  36
  37 -static int ar71xx_pci_check_error(int quiet)
  38 +static inline struct ar71xx_pci_controller *
  39 +pci_bus_to_ar71xx_controller(struct pci_bus *bus)
  40  {
  41 -       void __iomem *base = ar71xx_pcicfg_base;
  42 +       struct pci_controller *hose;
  43 +
  44 +       hose = (struct pci_controller *) bus->sysdata;
  45 +       return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
  46 +}
  47 +
  48 +static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
  49 +{
  50 +       void __iomem *base = apc->cfg_base;
  51         u32 pci_err;
  52         u32 ahb_err;
  53
  54 @@ -129,9 +142,10 @@ static int ar71xx_pci_check_error(int qu
  55         return !!(ahb_err | pci_err);
  56  }
  57
  58 -static inline void ar71xx_pci_local_write(int where, int size, u32 value)
  59 +static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
  60 +                                         int where, int size, u32 value)
  61  {
  62 -       void __iomem *base = ar71xx_pcicfg_base;
  63 +       void __iomem *base = apc->cfg_base;
  64         u32 ad_cbe;
  65
  66         value = value << (8 * (where & 3));
  67 @@ -147,7 +161,8 @@ static inline int ar71xx_pci_set_cfgaddr
  68                                          unsigned int devfn,
  69                                          int where, int size, u32 cmd)
  70  {
  71 -       void __iomem *base = ar71xx_pcicfg_base;
  72 +       struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
  73 +       void __iomem *base = apc->cfg_base;
  74         u32 addr;
  75
  76         addr = ar71xx_pci_bus_addr(bus, devfn, where);
  77 @@ -156,13 +171,14 @@ static inline int ar71xx_pci_set_cfgaddr
  78         __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
  79                      base + AR71XX_PCI_REG_CFG_CBE);
  80
  81 -       return ar71xx_pci_check_error(1);
  82 +       return ar71xx_pci_check_error(apc, 1);
  83  }
  84
  85  static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  86                                   int where, int size, u32 *value)
  87  {
  88 -       void __iomem *base = ar71xx_pcicfg_base;
  89 +       struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
  90 +       void __iomem *base = apc->cfg_base;
  91         unsigned long flags;
  92         u32 data;
  93         int err;
  94 @@ -171,7 +187,7 @@ static int ar71xx_pci_read_config(struct
  95         ret = PCIBIOS_SUCCESSFUL;
  96         data = ~0;
  97
  98 -       spin_lock_irqsave(&ar71xx_pci_lock, flags);
  99 +       spin_lock_irqsave(&apc->lock, flags);
 100
 101         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 102                                      AR71XX_PCI_CFG_CMD_READ);
 103 @@ -180,7 +196,7 @@ static int ar71xx_pci_read_config(struct
 104         else
 105                 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
 106
 107 -       spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 108 +       spin_unlock_irqrestore(&apc->lock, flags);
 109
 110         *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
 111
 112 @@ -190,7 +206,8 @@ static int ar71xx_pci_read_config(struct
 113  static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 114                                    int where, int size, u32 value)
 115  {
 116 -       void __iomem *base = ar71xx_pcicfg_base;
 117 +       struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 118 +       void __iomem *base = apc->cfg_base;
 119         unsigned long flags;
 120         int err;
 121         int ret;
 122 @@ -198,7 +215,7 @@ static int ar71xx_pci_write_config(struc
 123         value = value << (8 * (where & 3));
 124         ret = PCIBIOS_SUCCESSFUL;
 125
 126 -       spin_lock_irqsave(&ar71xx_pci_lock, flags);
 127 +       spin_lock_irqsave(&apc->lock, flags);
 128
 129         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 130                                      AR71XX_PCI_CFG_CMD_WRITE);
 131 @@ -207,7 +224,7 @@ static int ar71xx_pci_write_config(struc
 132         else
 133                 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
 134
 135 -       spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 136 +       spin_unlock_irqrestore(&apc->lock, flags);
 137
 138         return ret;
 139  }
 140 @@ -231,12 +248,6 @@ static struct resource ar71xx_pci_mem_re
 141         .flags          = IORESOURCE_MEM
 142  };
 143
 144 -static struct pci_controller ar71xx_pci_controller = {
 145 -       .pci_ops        = &ar71xx_pci_ops,
 146 -       .mem_resource   = &ar71xx_pci_mem_resource,
 147 -       .io_resource    = &ar71xx_pci_io_resource,
 148 -};
 149 -
 150  static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 151  {
 152         void __iomem *base = ath79_reset_base;
 153 @@ -294,7 +305,7 @@ static struct irq_chip ar71xx_pci_irq_ch
 154         .irq_mask_ack   = ar71xx_pci_irq_mask,
 155  };
 156
 157 -static void ar71xx_pci_irq_init(int irq)
 158 +static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
 159  {
 160         void __iomem *base = ath79_reset_base;
 161         int i;
 162 @@ -309,7 +320,7 @@ static void ar71xx_pci_irq_init(int irq)
 163                 irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
 164                                          handle_level_irq);
 165
 166 -       irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
 167 +       irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
 168  }
 169
 170  static void ar71xx_pci_reset(void)
 171 @@ -336,20 +347,27 @@ static void ar71xx_pci_reset(void)
 172
 173  static int ar71xx_pci_probe(struct platform_device *pdev)
 174  {
 175 +       struct ar71xx_pci_controller *apc;
 176         struct resource *res;
 177 -       int irq;
 178         u32 t;
 179
 180 +       apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
 181 +                          GFP_KERNEL);
 182 +       if (!apc)
 183 +               return -ENOMEM;
 184 +
 185 +       spin_lock_init(&apc->lock);
 186 +
 187         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
 188         if (!res)
 189                 return -EINVAL;
 190
 191 -       ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
 192 -       if (!ar71xx_pcicfg_base)
 193 +       apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
 194 +       if (!apc->cfg_base)
 195                 return -ENOMEM;
 196
 197 -       irq = platform_get_irq(pdev, 0);
 198 -       if (irq < 0)
 199 +       apc->irq = platform_get_irq(pdev, 0);
 200 +       if (apc->irq < 0)
 201                 return -EINVAL;
 202
 203         ar71xx_pci_reset();
 204 @@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platf
 205         /* setup COMMAND register */
 206         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 207           | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 208 -       ar71xx_pci_local_write(PCI_COMMAND, 4, t);
 209 +       ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
 210
 211         /* clear bus errors */
 212 -       ar71xx_pci_check_error(1);
 213 +       ar71xx_pci_check_error(apc, 1);
 214 +
 215 +       ar71xx_pci_irq_init(apc);
 216
 217 -       ar71xx_pci_irq_init(irq);
 218 +       apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 219 +       apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
 220 +       apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
 221
 222 -       register_pci_controller(&ar71xx_pci_controller);
 223 +       register_pci_controller(&apc->pci_ctrl);
 224
 225         return 0;
 226  }