target/linux/ar71xx/patches-4.1/622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch

   1 --- a/arch/mips/ath79/dev-eth.c
   2 +++ b/arch/mips/ath79/dev-eth.c
   3 @@ -198,7 +198,6 @@ void __init ath79_register_mdio(unsigned
   4         case ATH79_SOC_AR9330:
   5         case ATH79_SOC_AR9331:
   6         case ATH79_SOC_QCA9533:
   7 -       case ATH79_SOC_QCA9561:
   8         case ATH79_SOC_TP9343:
   9                 mdio_dev = &ath79_mdio1_device;
  10                 mdio_data = &ath79_mdio1_data;
  11 @@ -209,6 +208,7 @@ void __init ath79_register_mdio(unsigned
  12         case ATH79_SOC_AR9344:
  13         case ATH79_SOC_QCA9556:
  14         case ATH79_SOC_QCA9558:
  15 +       case ATH79_SOC_QCA956X:
  16                 if (id == 0) {
  17                         mdio_dev = &ath79_mdio0_device;
  18                         mdio_data = &ath79_mdio0_data;
  19 @@ -258,7 +258,6 @@ void __init ath79_register_mdio(unsigned
  20                 break;
  21
  22         case ATH79_SOC_QCA9533:
  23 -       case ATH79_SOC_QCA9561:
  24         case ATH79_SOC_TP9343:
  25                 mdio_data->builtin_switch = 1;
  26                 break;
  27 @@ -268,6 +267,11 @@ void __init ath79_register_mdio(unsigned
  28                 mdio_data->is_ar934x = 1;
  29                 break;
  30
  31 +       case ATH79_SOC_QCA956X:
  32 +               if (id == 1)
  33 +                       mdio_data->builtin_switch = 1;
  34 +               break;
  35 +
  36         default:
  37                 break;
  38         }
  39 @@ -387,6 +391,16 @@ static void qca955x_set_speed_sgmii(int
  40         iounmap(base);
  41  }
  42
  43 +static void qca956x_set_speed_sgmii(int speed)
  44 +{
  45 +       void __iomem *base;
  46 +       u32 val = ath79_get_eth_pll(0, speed);
  47 +
  48 +       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  49 +       __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
  50 +       iounmap(base);
  51 +}
  52 +
  53  static void ath79_set_speed_dummy(int speed)
  54  {
  55  }
  56 @@ -517,6 +531,10 @@ struct ag71xx_switch_platform_data ath79
  57  #define AR934X_PLL_VAL_100     0x00000101
  58  #define AR934X_PLL_VAL_10      0x00001616
  59
  60 +#define QCA956X_PLL_VAL_1000   0x03000000
  61 +#define QCA956X_PLL_VAL_100    0x00000101
  62 +#define QCA956X_PLL_VAL_10     0x00001919
  63 +
  64  static void __init ath79_init_eth_pll_data(unsigned int id)
  65  {
  66         struct ath79_eth_pll_data *pll_data;
  67 @@ -575,13 +593,18 @@ static void __init ath79_init_eth_pll_da
  68         case ATH79_SOC_QCA9533:
  69         case ATH79_SOC_QCA9556:
  70         case ATH79_SOC_QCA9558:
  71 -       case ATH79_SOC_QCA9561:
  72         case ATH79_SOC_TP9343:
  73                 pll_10 = AR934X_PLL_VAL_10;
  74                 pll_100 = AR934X_PLL_VAL_100;
  75                 pll_1000 = AR934X_PLL_VAL_1000;
  76                 break;
  77
  78 +       case ATH79_SOC_QCA956X:
  79 +               pll_10 = QCA956X_PLL_VAL_10;
  80 +               pll_100 = QCA956X_PLL_VAL_100;
  81 +               pll_1000 = QCA956X_PLL_VAL_1000;
  82 +               break;
  83 +
  84         default:
  85                 BUG();
  86         }
  87 @@ -656,6 +679,7 @@ static int __init ath79_setup_phy_if_mod
  88
  89                 case ATH79_SOC_QCA9556:
  90                 case ATH79_SOC_QCA9558:
  91 +               case ATH79_SOC_QCA956X:
  92                         switch (pdata->phy_if_mode) {
  93                         case PHY_INTERFACE_MODE_MII:
  94                         case PHY_INTERFACE_MODE_RGMII:
  95 @@ -666,11 +690,6 @@ static int __init ath79_setup_phy_if_mod
  96                         }
  97                         break;
  98
  99 -               case ATH79_SOC_QCA9561:
 100 -                       if (!pdata->phy_if_mode)
 101 -                               pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
 102 -                       break;
 103 -
 104                 default:
 105                         BUG();
 106                 }
 107 @@ -699,7 +718,7 @@ static int __init ath79_setup_phy_if_mod
 108                 case ATH79_SOC_AR7241:
 109                 case ATH79_SOC_AR9330:
 110                 case ATH79_SOC_AR9331:
 111 -               case ATH79_SOC_QCA9561:
 112 +               case ATH79_SOC_QCA956X:
 113                 case ATH79_SOC_TP9343:
 114                         pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
 115                         break;
 116 @@ -1032,7 +1051,6 @@ void __init ath79_register_eth(unsigned
 117                         pdata->fifo_cfg3 = 0x01f00140;
 118                 break;
 119
 120 -       case ATH79_SOC_QCA9561:
 121         case ATH79_SOC_TP9343:
 122                 if (id == 0) {
 123                         pdata->reset_bit = AR933X_RESET_GE0_MAC |
 124 @@ -1100,6 +1118,34 @@ void __init ath79_register_eth(unsigned
 125                         pdata->fifo_cfg3 = 0x01f00140;
 126                 break;
 127
 128 +       case ATH79_SOC_QCA956X:
 129 +               if (id == 0) {
 130 +                       pdata->reset_bit = QCA955X_RESET_GE0_MAC |
 131 +                                          QCA955X_RESET_GE0_MDIO;
 132 +                       if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
 133 +                               pdata->set_speed = qca956x_set_speed_sgmii;
 134 +                       else
 135 +                               /* FIXME */
 136 +                               pdata->set_speed = ath79_set_speed_dummy;
 137 +               } else {
 138 +                       pdata->reset_bit = QCA955X_RESET_GE1_MAC |
 139 +                                          QCA955X_RESET_GE1_MDIO;
 140 +                       /* FIXME */
 141 +                       pdata->set_speed = ath79_set_speed_dummy;
 142 +               }
 143 +
 144 +               pdata->ddr_flush = ath79_ddr_no_flush;
 145 +               pdata->has_gbit = 1;
 146 +               pdata->is_ar724x = 1;
 147 +
 148 +               if (!pdata->fifo_cfg1)
 149 +                       pdata->fifo_cfg1 = 0x0010ffff;
 150 +               if (!pdata->fifo_cfg2)
 151 +                       pdata->fifo_cfg2 = 0x015500aa;
 152 +               if (!pdata->fifo_cfg3)
 153 +                       pdata->fifo_cfg3 = 0x01f00140;
 154 +               break;
 155 +
 156         default:
 157                 BUG();
 158         }
 159 @@ -1140,7 +1186,6 @@ void __init ath79_register_eth(unsigned
 160                 case ATH79_SOC_AR9330:
 161                 case ATH79_SOC_AR9331:
 162                 case ATH79_SOC_QCA9533:
 163 -               case ATH79_SOC_QCA9561:
 164                 case ATH79_SOC_TP9343:
 165                         pdata->mii_bus_dev = &ath79_mdio1_device.dev;
 166                         break;