1 Index: linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
2 ===================================================================
3 --- linux-4.9.111.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
4 +++ linux-4.9.111/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
6 #define QCA955X_PCI_CTRL_SIZE 0x100
8 #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
9 -#define QCA955X_GMAC_SIZE 0x40
10 +#define QCA955X_GMAC_SIZE 0x64
11 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
12 #define QCA955X_WMAC_SIZE 0x20000
13 #define QCA955X_EHCI0_BASE 0x1b000000
14 @@ -1269,7 +1269,11 @@
17 #define QCA955X_GMAC_REG_ETH_CFG 0x00
18 +#define QCA955X_GMAC_REG_SGMII_RESET 0x14
19 #define QCA955X_GMAC_REG_SGMII_SERDES 0x18
20 +#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
21 +#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20
22 +#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58
24 #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
25 #define QCA955X_ETH_CFG_MII_GE0 BIT(1)
26 @@ -1291,6 +1295,18 @@
27 #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
28 #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
30 +#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0x0
31 +#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0)
32 +#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1)
33 +#define QCA955X_SGMII_RESET_RX_125M_N BIT(2)
34 +#define QCA955X_SGMII_RESET_TX_125M_N BIT(3)
35 +#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4)
37 +#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15)
38 +#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12)
40 +#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3)
42 #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
43 #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
44 #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf