target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch

   1 From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Wed, 9 Dec 2020 15:03:33 +0200
   4 Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate
   5
   6 SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or
   7 by the external clock provided by the PHY. The internal IP logic divides
   8 properly this clock depending on the link speed. The patch adds a new
   9 capability so that macb_set_tx_clock() to not be called for IPs having
  10 this capability (the clock rate, in case of generic clock, is set at the
  11 boot time via device tree and the driver only enables it).
  12
  13 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  14 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  15 Signed-off-by: David S. Miller <davem@davemloft.net>
  16 ---
  17  drivers/net/ethernet/cadence/macb.h      |  1 +
  18  drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++---------
  19  2 files changed, 10 insertions(+), 9 deletions(-)
  20
  21 --- a/drivers/net/ethernet/cadence/macb.h
  22 +++ b/drivers/net/ethernet/cadence/macb.h
  23 @@ -658,6 +658,7 @@
  24  #define MACB_CAPS_GEM_HAS_PTP                  0x00000040
  25  #define MACB_CAPS_BD_RD_PREFETCH               0x00000080
  26  #define MACB_CAPS_NEEDS_RSTONUBR               0x00000100
  27 +#define MACB_CAPS_CLK_HW_CHG                   0x04000000
  28  #define MACB_CAPS_MACB_IS_EMAC                 0x08000000
  29  #define MACB_CAPS_FIFO_MODE                    0x10000000
  30  #define MACB_CAPS_GIGABIT_MODE_AVAILABLE       0x20000000
  31 --- a/drivers/net/ethernet/cadence/macb_main.c
  32 +++ b/drivers/net/ethernet/cadence/macb_main.c
  33 @@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac
  34
  35  /**
  36   * macb_set_tx_clk() - Set a clock to a new frequency
  37 - * @clk:       Pointer to the clock to change
  38 + * @bp:                pointer to struct macb
  39   * @speed:     New frequency in Hz
  40 - * @dev:       Pointer to the struct net_device
  41   */
  42 -static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
  43 +static void macb_set_tx_clk(struct macb *bp, int speed)
  44  {
  45         long ferr, rate, rate_rounded;
  46
  47 -       if (!clk)
  48 +       if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
  49                 return;
  50
  51         switch (speed) {
  52 @@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk *
  53                 return;
  54         }
  55
  56 -       rate_rounded = clk_round_rate(clk, rate);
  57 +       rate_rounded = clk_round_rate(bp->tx_clk, rate);
  58         if (rate_rounded < 0)
  59                 return;
  60
  61 @@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk *
  62         ferr = abs(rate_rounded - rate);
  63         ferr = DIV_ROUND_UP(ferr, rate / 100000);
  64         if (ferr > 5)
  65 -               netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
  66 +               netdev_warn(bp->dev,
  67 +                           "unable to generate target frequency: %ld Hz\n",
  68                             rate);
  69
  70 -       if (clk_set_rate(clk, rate_rounded))
  71 -               netdev_err(dev, "adjusting tx_clk failed.\n");
  72 +       if (clk_set_rate(bp->tx_clk, rate_rounded))
  73 +               netdev_err(bp->dev, "adjusting tx_clk failed.\n");
  74  }
  75
  76  static void macb_validate(struct phylink_config *config,
  77 @@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl
  78                 if (rx_pause)
  79                         ctrl |= MACB_BIT(PAE);
  80
  81 -               macb_set_tx_clk(bp->tx_clk, speed, ndev);
  82 +               macb_set_tx_clk(bp, speed);
  83
  84                 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
  85                  * cleared the pipeline and control registers.