1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,ar7100";
9 bootargs = "console=ttyS0,115200";
18 compatible = "mips,mips24Kc";
19 clocks = <&pll ATH79_CLK_CPU>;
25 compatible = "fixed-clock";
27 clock-output-names = "ref";
28 clock-frequency = <40000000>;
33 ddr_ctrl: memory-controller@18000000 {
34 compatible = "qca,ar7100-ddr-controller";
35 reg = <0x18000000 0x100>;
37 #qca,ddr-wb-channel-cells = <1>;
41 compatible = "ns16550a";
42 reg = <0x18020000 0x20>;
45 clocks = <&pll ATH79_CLK_AHB>;
53 usb_phy: usb-phy@18030000 {
54 compatible = "qca,ar7100-usb-phy";
55 reg = <0x18030000 0x10>;
57 reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
58 resets = <&rst 4>, <&rst 5>, <&rst 6>;
66 compatible = "qca,ar7100-gpio";
67 reg = <0x18040000 0x28>;
76 #interrupt-cells = <2>;
79 pll: pll-controller@18050000 {
80 compatible = "qca,ar7100-pll", "syscon";
81 reg = <0x18050000 0x20>;
87 clock-output-names = "cpu", "ddr", "ahb";
91 compatible = "qca,ar7130-wdt";
92 reg = <0x18060008 0x8>;
96 clocks = <&pll ATH79_CLK_AHB>;
100 pci_intc: interrupt-controller@18060018 {
101 compatible = "qca,ar7100-misc-intc";
102 reg = <0x18060018 0x4>;
103 interrupt-parent = <&cpuintc>;
105 interrupt-controller;
106 #interrupt-cells = <1>;
109 rst: reset-controller@18060024 {
110 compatible = "qca,ar7100-reset";
111 reg = <0x18060024 0x4>;
116 pcie0: pcie-controller@17010000 {
117 compatible = "qca,ar7100-pci";
118 #address-cells = <3>;
120 bus-range = <0x0 0x0>;
121 reg = <0x17010000 0x100>;
122 reg-names = "cfg_base";
123 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
124 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
128 interrupt-parent = <&pci_intc>;
131 #interrupt-cells = <1>;
133 interrupt-map-mask = <0xf800 0 0 0>;
134 interrupt-map = <0x8800 0 0 0 &pci_intc 0
135 0x9000 0 0 0 &pci_intc 1
136 0x9800 0 0 0 &pci_intc 2>;
144 compatible = "generic-ehci";
145 reg = <0x1b000000 0x1000>;
147 interrupt-parent = <&cpuintc>;
150 phy-names = "usb-phy";
157 #address-cells = <1>;
160 usb_ehci_port: port@1 {
162 #trigger-source-cells = <0>;
167 compatible = "generic-ohci";
168 reg = <0x1c000000 0x1000>;
170 interrupt-parent = <&miscintc>;
173 phy-names = "usb-phy";
178 #address-cells = <1>;
181 usb_ohci_port: port@1 {
183 #trigger-source-cells = <0>;
188 compatible = "qca,ar7100-spi";
189 reg = <0x1f000000 0x10>;
191 clocks = <&pll ATH79_CLK_AHB>;
194 #address-cells = <1>;
202 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
203 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
204 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
208 compatible = "qca,ar7100-misc-intc";
212 compatible = "qca,ar7100-eth", "syscon";
213 reg = <0x19000000 0x200
216 pll-data = <0x00110000 0x00001099 0x00991099>;
217 pll-reg = <0x4 0x10 17>;
231 compatible = "qca,ar7100-eth", "syscon";
232 reg = <0x1a000000 0x200
235 pll-data = <0x00110000 0x00001099 0x00991099>;
236 pll-reg = <0x4 0x14 19>;