1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,ar7240";
12 bootargs = "console=ttyS0,115200";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
29 ddr_ctrl: memory-controller@18000000 {
30 compatible = "qca,ar9132-ddr-controller",
31 "qca,ar7240-ddr-controller";
32 reg = <0x18000000 0x100>;
34 #qca,ddr-wb-channel-cells = <1>;
38 compatible = "ns16550a";
39 reg = <0x18020000 0x20>;
42 clocks = <&pll ATH79_CLK_AHB>;
51 compatible = "qca,ar7240-gpio",
53 reg = <0x18040000 0x30>;
62 #interrupt-cells = <2>;
65 pinmux: pinmux@18040028 {
66 compatible = "pinctrl-single";
68 reg = <0x18040028 0x8>;
70 pinctrl-single,bit-per-mux;
71 pinctrl-single,register-width = <32>;
72 pinctrl-single,function-mask = <0x1>;
75 jtag_disable_pins: pinmux_jtag_disable_pins {
76 pinctrl-single,bits = <0x0 0x1 0x1>;
79 switch_led_disable_pins: pinmux_switch_led_disable_pins {
80 pinctrl-single,bits = <0x0 0x0 0xf8>;
83 clks_disable_pins: pinmux_clks_disable_pins {
84 pinctrl-single,bits = <0x0 0x0 0x81f00>;
88 pll: pll-controller@18050000 {
89 compatible = "qca,ar7240-pll", "syscon";
90 reg = <0x18050000 0x3c>;
93 /* The board must provides the ref clock */
96 clock-output-names = "cpu", "ddr", "ahb";
100 compatible = "qca,ar7130-wdt";
101 reg = <0x18060008 0x8>;
105 clocks = <&pll ATH79_CLK_AHB>;
109 rst: reset-controller@1806001c {
110 compatible = "qca,ar7240-reset",
112 reg = <0x1806001c 0x4>;
117 pcie: pcie-controller@180c0000 {
118 compatible = "qcom,ar7240-pci";
119 #address-cells = <3>;
121 bus-range = <0x0 0x0>;
122 reg = <0x180c0000 0x1000>, /* CRP */
123 <0x180f0000 0x100>, /* CTRL */
124 <0x14000000 0x1000>; /* CFG */
125 reg-names = "crp_base", "ctrl_base", "cfg_base";
126 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
127 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
128 interrupt-parent = <&cpuintc>;
131 resets = <&rst 6>, <&rst 7>;
132 reset-names = "hc", "phy";
136 interrupt-controller;
137 #interrupt-cells = <1>;
139 interrupt-map-mask = <0 0 0 1>;
140 interrupt-map = <0 0 0 0 &pcie 0>;
146 compatible = "qca,ar7240-spi",
148 reg = <0x1f000000 0x10>;
150 clocks = <&pll ATH79_CLK_AHB>;
155 #address-cells = <1>;
162 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
163 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
164 <&ddr_ctrl 0>, <&ddr_ctrl 1>;