1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
6 compatible = "qca,ar7240";
12 bootargs = "console=ttyS0,115200";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
29 ddr_ctrl: memory-controller@18000000 {
30 compatible = "qca,ar9132-ddr-controller",
31 "qca,ar7240-ddr-controller";
32 reg = <0x18000000 0x100>;
34 #qca,ddr-wb-channel-cells = <1>;
38 compatible = "ns16550a";
39 reg = <0x18020000 0x20>;
42 clocks = <&pll ATH79_CLK_AHB>;
53 compatible = "qca,ar7240-gpio",
55 reg = <0x18040000 0x30>;
64 #interrupt-cells = <2>;
67 pll: pll-controller@18050000 {
68 compatible = "qca,ar7240-pll",
70 reg = <0x18050000 0x20>;
73 /* The board must provides the ref clock */
76 clock-output-names = "cpu", "ddr", "ahb";
80 compatible = "qca,ar7130-wdt";
81 reg = <0x18060008 0x8>;
85 clocks = <&pll ATH79_CLK_AHB>;
89 rst: reset-controller@1806001c {
90 compatible = "qca,ar7240-reset",
92 reg = <0x1806001c 0x4>;
97 pcie: pcie-controller@180c0000 {
98 compatible = "qcom,ar7240-pci";
101 bus-range = <0x0 0x0>;
102 reg = <0x180c0000 0x1000>, /* CRP */
103 <0x180f0000 0x100>, /* CTRL */
104 <0x14000000 0x1000>; /* CFG */
105 reg-names = "crp_base", "ctrl_base", "cfg_base";
106 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
107 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
108 interrupt-parent = <&cpuintc>;
111 interrupt-controller;
112 #interrupt-cells = <1>;
114 interrupt-map-mask = <0 0 0 1>;
115 interrupt-map = <0 0 0 0 &pcie 0>;
121 compatible = "qca,ar7240-spi",
123 reg = <0x1f000000 0x10>;
125 clocks = <&pll ATH79_CLK_AHB>;
130 #address-cells = <1>;
137 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
138 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
139 <&ddr_ctrl 0>, <&ddr_ctrl 1>;