1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,ar9330";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
28 bootargs = "console=ttyATH0,115200";
32 compatible = "fixed-clock";
34 clock-output-names = "ref";
39 ddr_ctrl: memory-controller@18000000 {
40 compatible = "qca,ar7240-ddr-controller";
41 reg = <0x18000000 0x100>;
43 #qca,ddr-wb-channel-cells = <1>;
47 compatible = "qca,ar9330-uart";
48 reg = <0x18020000 0x14>;
52 clocks = <&pll ATH79_CLK_REF>;
57 compatible = "qca,ar7100-gpio";
58 reg = <0x18040000 0x28>;
67 #interrupt-cells = <2>;
70 pinmux: pinmux@18040028 {
71 compatible = "pinctrl-single";
72 reg = <0x18040028 0x8>;
74 pinctrl-single,bit-per-mux;
75 pinctrl-single,register-width = <32>;
76 pinctrl-single,function-mask = <0x1>;
79 jtag_disable_pins: pinmux_jtag_disable_pins {
80 pinctrl-single,bits = <0x0 0x1 0x1>;
83 switch_led_disable_pins: pinmux_switch_led_disable_pins {
84 pinctrl-single,bits = <0x0 0x0 0xf8>;
88 pll: pll-controller@18050000 {
89 compatible = "qca,ar9330-pll";
90 reg = <0x18050000 0x100>;
96 clock-output-names = "cpu", "ddr", "ahb";
100 compatible = "qca,ar7130-wdt";
101 reg = <0x18060008 0x8>;
105 clocks = <&pll ATH79_CLK_AHB>;
109 rst: reset-controller@1806001c {
110 compatible = "qca,ar7100-reset";
111 reg = <0x1806001c 0x4>;
118 compatible = "chipidea,usb2";
119 reg = <0x1b000000 0x200>;
123 reset-names = "usb-host";
125 phy-names = "usb-phy";
130 #address-cells = <1>;
135 #trigger-source-cells = <0>;
140 compatible = "qca,ar934x-spi";
141 reg = <0x1f000000 0x1c>;
143 clocks = <&pll ATH79_CLK_AHB>;
145 #address-cells = <1>;
151 gmac: gmac@18070000 {
152 compatible = "qca,ar9330-gmac";
153 reg = <0x18070000 0x4>;
156 wmac: wmac@18100000 {
157 compatible = "qca,ar9330-wmac";
158 reg = <0x18100000 0x20000>;
167 compatible = "qca,ar7200-usb-phy";
169 reset-names = "usb-phy", "usb-suspend-override";
170 resets = <&rst 4>, <&rst 3>;
179 qca,ddr-wb-channel-interrupts = <2>, <3>;
180 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
184 compatible = "qca,ar9330-eth", "syscon";
186 pll-data = <0x00110000 0x00001099 0x00991099>;
190 phy-handle = <&swphy4>;
195 compatible = "qca,ar9330-mdio";
198 reset-names = "mdio";
201 builtin_switch: switch0@1f {
202 compatible = "qca,ar7240sw";
205 reset-names = "switch";
206 qca,mib-poll-interval = <500>;
209 #address-cells = <1>;
212 swphy4: ethernet-phy@4 {
221 compatible = "qca,ar9330-eth", "syscon";
223 pll-data = <0x00110000 0x00001099 0x00991099>;