ath79: add support for GL.iNet GL-XE300
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9531_glinet_gl-xe300.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca953x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "glinet,gl-xe300", "qca,qca9531";
10 model = "GL.iNet GL-XE300";
11
12 gpio-export {
13 compatible = "gpio-export";
14
15 gpio_lte_power {
16 gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
17 gpio-export,name = "lte_power";
18 gpio-export,output = <1>;
19 };
20
21 gpio_sd_detect {
22 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
23 gpio-export,name = "sd_detect";
24 gpio-export,output = <0>;
25 };
26 };
27
28 keys {
29 compatible = "gpio-keys";
30
31 pinctrl-names = "default";
32 pinctrl-0 = <&jtag_disable_pins>;
33
34 reset {
35 label = "reset";
36 linux,code = <KEY_RESTART>;
37 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
38 };
39 };
40
41 leds {
42 compatible = "gpio-leds";
43
44 lan {
45 gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
46 label = "green:lan";
47 };
48
49 wan {
50 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
51 label = "green:wan";
52 };
53
54 wlan {
55 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
56 label = "green:wlan";
57 linux,default-trigger = "phy0tpt";
58 };
59
60 lte {
61 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
62 label = "green:lte";
63 };
64 };
65 };
66
67 &pcie0 {
68 status = "okay";
69 };
70
71 &usb0 {
72 status = "okay";
73 };
74
75 &usb_phy {
76 status = "okay";
77 };
78
79 &spi {
80 status = "okay";
81
82 flash@0 {
83 compatible = "jedec,spi-nor";
84 reg = <0>;
85 spi-max-frequency = <25000000>;
86
87 partitions {
88 compatible = "fixed-partitions";
89 #address-cells = <1>;
90 #size-cells = <1>;
91
92 partition@0 {
93 label = "u-boot";
94 reg = <0x0 0x40000>;
95 read-only;
96 };
97
98 partition@40000 {
99 label = "u-boot-env";
100 reg = <0x40000 0x10000>;
101 };
102
103 art: partition@50000 {
104 label = "art";
105 reg = <0x50000 0x10000>;
106 read-only;
107 };
108
109 partition@60000 {
110 label = "kernel";
111 reg = <0x60000 0x400000>;
112 };
113
114 partition@460000 {
115 label = "nor_reserved";
116 reg = <0x460000 0xba0000>;
117 };
118 };
119 };
120
121 flash@1 {
122 compatible = "spi-nand";
123 reg = <1>;
124 spi-max-frequency = <25000000>;
125
126 partitions {
127 compatible = "fixed-partitions";
128 #address-cells = <1>;
129 #size-cells = <1>;
130
131 partition@0 {
132 label = "ubi";
133 reg = <0x0 0x8000000>;
134 };
135 };
136 };
137 };
138
139 &eth0 {
140 status = "okay";
141
142 phy-handle = <&swphy4>;
143
144 nvmem-cells = <&macaddr_art_0>;
145 nvmem-cell-names = "mac-address";
146 mtd-mac-address-increment = <1>;
147 };
148
149 &eth1 {
150 nvmem-cells = <&macaddr_art_0>;
151 nvmem-cell-names = "mac-address";
152 };
153
154 &wmac {
155 status = "okay";
156
157 mtd-cal-data = <&art 0x1000>;
158 };
159
160 &art {
161 compatible = "nvmem-cells";
162 #address-cells = <1>;
163 #size-cells = <1>;
164
165 macaddr_art_0: macaddr@0 {
166 reg = <0x0 0x6>;
167 };
168 };