1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 compatible = "qca,qca9530";
12 bootargs = "console=ttyS0,115200n8";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
28 compatible = "fixed-clock";
30 clock-output-names = "ref";
31 clock-frequency = <25000000>;
36 ddr_ctrl: memory-controller@18000000 {
37 compatible = "qca,qca9530-ddr-controller",
38 "qca,ar7240-ddr-controller";
39 reg = <0x18000000 0x128>;
41 #qca,ddr-wb-channel-cells = <1>;
45 compatible = "ns16550a";
46 reg = <0x18020000 0x20>;
50 clocks = <&pll ATH79_CLK_REF>;
58 usb_phy: usb-phy@18030000 {
59 compatible = "qca,ar7200-usb-phy";
60 reg = <0x18030000 0x100>;
63 reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
64 resets = <&rst 11>, <&rst 4>, <&rst 3>;
70 compatible = "qca,qca9530-gpio",
72 reg = <0x18040000 0x28>;
81 #interrupt-cells = <2>;
84 pinmux: pinmux@1804002c {
85 compatible = "pinctrl-single";
87 reg = <0x1804002c 0x48>;
91 pinctrl-single,bit-per-mux;
92 pinctrl-single,register-width = <32>;
93 pinctrl-single,function-mask = <0x1>;
96 jtag_disable_pins: pinmux_jtag_disable_pins {
97 pinctrl-single,bits = <0x40 0x2 0x2>;
101 pll: pll-controller@18050000 {
102 compatible = "qca,qca9530-pll", "syscon";
103 reg = <0x18050000 0x48>;
106 clock-output-names = "cpu", "ddr", "ahb";
113 compatible = "qca,qca9530-wdt", "qca,ar7130-wdt";
114 reg = <0x18060008 0x8>;
118 clocks = <&pll ATH79_CLK_AHB>;
122 rst: reset-controller@1806001c {
123 compatible = "qca,qca9530-reset",
125 reg = <0x1806001c 0xac>;
129 intc2: interrupt-controller {
130 compatible = "qca,ar9340-intc";
132 interrupt-parent = <&cpuintc>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
138 qca,int-status-addr = <0xac>;
139 qca,pending-bits = <0xf>, /* wmac */
140 <0x1f0>; /* pcie rc1 */
142 qca,ddr-wb-channel-interrupts = <0>, <1>;
143 qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;
148 gmac: gmac@18070000 {
149 compatible = "qca,ar9330-gmac";
150 reg = <0x18070000 0x4>;
153 pcie0: pcie-controller@180c0000 {
154 compatible = "qcom,ar7240-pci";
155 #address-cells = <3>;
157 bus-range = <0x0 0x0>;
158 reg = <0x180c0000 0x1000>, /* CRP */
159 <0x180f0000 0x100>, /* CTRL */
160 <0x14000000 0x1000>; /* CFG */
161 reg-names = "crp_base", "ctrl_base", "cfg_base";
162 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
163 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
164 interrupt-parent = <&intc2>;
169 resets = <&rst 6>, <&rst 7>;
170 reset-names = "hc", "phy";
172 interrupt-controller;
173 #interrupt-cells = <1>;
175 interrupt-map-mask = <0 0 0 1>;
176 interrupt-map = <0 0 0 0 &pcie0 0>;
180 wmac: wmac@18100000 {
181 compatible = "qca,qca9530-wmac";
182 reg = <0x18100000 0x20000>;
184 interrupt-parent = <&intc2>;
191 compatible = "generic-ehci";
192 reg = <0x1b000000 0x1000>;
196 reset-names = "usb-host";
199 has-transaction-translator;
200 caps-offset = <0x100>;
202 phy-names = "usb-phy";
207 #address-cells = <1>;
212 #trigger-source-cells = <0>;
217 compatible = "qca,ar934x-spi";
218 reg = <0x1f000000 0x1c>;
220 clocks = <&pll ATH79_CLK_AHB>;
224 #address-cells = <1>;
231 qca,ddr-wb-channel-interrupts = <3>, <4>, <5>;
232 qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,
237 compatible = "qca,qca9530-eth", "syscon";
238 pll-data = <0x82000101 0x80000101 0x80001313>;
239 reg = <0x19000000 0x200
241 pll-reg = <0x4 0x2c 17>;
251 reset-names = "mdio";
254 builtin_switch: switch0@1f {
255 compatible = "qca,ar8229";
259 reset-names = "switch";
262 qca,mib-poll-interval = <500>;
265 #address-cells = <1>;
268 swphy0: ethernet-phy@0 {
273 swphy4: ethernet-phy@4 {
284 compatible = "qca,qca9530-eth", "syscon";