ath79: add support for TP-Link RE450 v3
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9563_tplink_re450.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 #include "qca956x.dtsi"
7
8 / {
9 chosen {
10 bootargs = "console=ttyS0,115200n8";
11 };
12
13 aliases {
14 led-boot = &led_power;
15 led-failsafe = &led_power;
16 led-running = &led_power;
17 led-upgrade = &led_power;
18 mdio-gpio0 = &mdio2;
19 };
20
21 leds {
22 compatible = "gpio-leds";
23
24 led_power: power {
25 label = "tp-link:blue:power";
26 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
27 };
28
29 wlan2g {
30 label = "tp-link:blue:wlan2g";
31 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
32 linux,default-trigger = "phy1tpt";
33 };
34
35 wlan5g {
36 label = "tp-link:blue:wlan5g";
37 gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
38 linux,default-trigger = "phy0tpt";
39 };
40
41 lan_link {
42 label = "tp-link:green:lan_link";
43 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
44 };
45
46 lan_data {
47 label = "tp-link:green:lan_data";
48 gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
49 };
50
51 wps_blue {
52 label = "tp-link:blue:wps";
53 gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
54 };
55
56 wps_red {
57 label = "tp-link:red:wps";
58 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
59 };
60 };
61
62 keys {
63 compatible = "gpio-keys";
64
65 reset {
66 label = "Reset button";
67 linux,code = <KEY_RESTART>;
68 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
69 debounce-interval = <60>;
70 };
71
72 power {
73 label = "Power button";
74 linux,code = <KEY_POWER>;
75 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
76 debounce-interval = <60>;
77 };
78
79 leds {
80 label = "LED control button";
81 linux,code = <BTN_0>;
82 gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
83 debounce-interval = <60>;
84 };
85
86 wps {
87 label = "WPS button";
88 linux,code = <KEY_WPS_BUTTON>;
89 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
90 debounce-interval = <60>;
91 };
92 };
93
94 mdio2: mdio {
95 compatible = "virtual,mdio-gpio";
96
97 gpios = <&gpio 3 GPIO_ACTIVE_HIGH>, /* MDC */
98 <&gpio 4 GPIO_ACTIVE_HIGH>; /* MDIO */
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 phy4: ethernet-phy@4 {
103 reg = <4>;
104 device_type = "ethernet-phy";
105 reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
106 };
107 };
108 };
109
110 &pcie {
111 status = "okay";
112 };
113
114 &uart {
115 status = "okay";
116 };
117
118 &gpio {
119 status = "okay";
120 };
121
122 &spi {
123 status = "okay";
124
125 num-cs = <1>;
126
127 flash@0 {
128 compatible = "jedec,spi-nor";
129 reg = <0>;
130 spi-max-frequency = <25000000>;
131
132 partitions: partitions {
133 compatible = "fixed-partitions";
134 #address-cells = <1>;
135 #size-cells = <1>;
136 };
137 };
138 };
139
140 &eth0 {
141 status = "okay";
142
143 phy-mode = "sgmii";
144 phy-handle = <&phy4>;
145
146 mtd-mac-address = <&info 0x8>;
147 };
148
149 &wmac {
150 status = "okay";
151
152 mtd-cal-data = <&art 0x1000>;
153 mtd-mac-address = <&info 0x8>;
154 };