2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/version.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/mtd/mtd.h>
17 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
18 #include <linux/mtd/nand.h>
20 #include <linux/mtd/rawnand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
26 #include <linux/of_device.h>
27 #include <linux/reset.h>
29 #define AR934X_NFC_DRIVER_NAME "ar934x-nand"
31 #define AR934X_NFC_REG_CMD 0x00
32 #define AR934X_NFC_REG_CTRL 0x04
33 #define AR934X_NFC_REG_STATUS 0x08
34 #define AR934X_NFC_REG_INT_MASK 0x0c
35 #define AR934X_NFC_REG_INT_STATUS 0x10
36 #define AR934X_NFC_REG_ECC_CTRL 0x14
37 #define AR934X_NFC_REG_ECC_OFFSET 0x18
38 #define AR934X_NFC_REG_ADDR0_0 0x1c
39 #define AR934X_NFC_REG_ADDR0_1 0x24
40 #define AR934X_NFC_REG_ADDR1_0 0x20
41 #define AR934X_NFC_REG_ADDR1_1 0x28
42 #define AR934X_NFC_REG_SPARE_SIZE 0x30
43 #define AR934X_NFC_REG_PROTECT 0x38
44 #define AR934X_NFC_REG_LOOKUP_EN 0x40
45 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
46 #define AR934X_NFC_REG_DMA_ADDR 0x64
47 #define AR934X_NFC_REG_DMA_COUNT 0x68
48 #define AR934X_NFC_REG_DMA_CTRL 0x6c
49 #define AR934X_NFC_REG_MEM_CTRL 0x80
50 #define AR934X_NFC_REG_DATA_SIZE 0x84
51 #define AR934X_NFC_REG_READ_STATUS 0x88
52 #define AR934X_NFC_REG_TIME_SEQ 0x8c
53 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
54 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
55 #define AR934X_NFC_REG_FIFO_DATA 0x98
56 #define AR934X_NFC_REG_TIME_MODE 0x9c
57 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
58 #define AR934X_NFC_REG_FIFO_INIT 0xb0
59 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
61 #define AR934X_NFC_CMD_CMD_SEQ_S 0
62 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
63 #define AR934X_NFC_CMD_SEQ_1C 0x00
64 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
65 #define AR934X_NFC_CMD_SEQ_12 0x0c
66 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
67 #define AR934X_NFC_CMD_SEQ_S 0x24
68 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
69 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
70 #define AR934X_NFC_CMD_SEQ_18 0x32
71 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
72 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
73 #define AR934X_NFC_CMD_ADDR_SEL_0 0
74 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
75 #define AR934X_NFC_CMD_CMD0_S 8
76 #define AR934X_NFC_CMD_CMD0_M 0xff
77 #define AR934X_NFC_CMD_CMD1_S 16
78 #define AR934X_NFC_CMD_CMD1_M 0xff
79 #define AR934X_NFC_CMD_CMD2_S 24
80 #define AR934X_NFC_CMD_CMD2_M 0xff
82 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
83 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
84 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
85 #define AR934X_NFC_CTRL_INT_EN BIT(4)
86 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
87 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
88 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
89 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
90 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
91 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
92 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
93 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
94 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
95 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
96 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
97 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
98 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
99 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
100 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
101 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
102 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
103 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
104 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
105 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
106 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
107 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
108 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
109 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
110 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
111 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
112 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
113 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
115 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
116 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
117 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
118 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
119 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
120 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
121 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
122 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
123 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
124 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
125 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
126 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
127 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
129 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
130 #define AR934X_NFC_INT_CMD_END BIT(1)
132 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
133 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
137 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
138 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
139 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
140 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
141 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
142 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
143 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
144 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
145 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
146 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
148 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
150 /* default timing values */
151 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
152 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
153 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
155 #define AR934X_NFC_ID_BUF_SIZE 8
156 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
157 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
158 #define AR934X_NFC_DONE_TIMEOUT 1000
159 #define AR934X_NFC_DMA_RETRIES 20
161 #define AR934X_NFC_USE_IRQ true
162 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
164 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
166 #undef AR934X_NFC_DEBUG_DATA
167 #undef AR934X_NFC_DEBUG
170 struct mtd_partition
;
174 struct nand_chip nand_chip
;
175 struct device
*parent
;
179 wait_queue_head_t irq_waitq
;
181 bool spurious_irq_expected
;
191 unsigned int addr_count0
;
192 unsigned int addr_count1
;
196 unsigned int buf_size
;
201 int erase1_page_addr
;
203 int rndout_page_addr
;
210 struct reset_control
*rst
;
213 static inline __printf(2, 3)
214 void _nfc_dbg(struct ar934x_nfc
*nfc
, const char *fmt
, ...)
218 #ifdef AR934X_NFC_DEBUG
219 #define nfc_dbg(_nfc, fmt, ...) \
220 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
222 #define nfc_dbg(_nfc, fmt, ...) \
223 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
224 #endif /* AR934X_NFC_DEBUG */
226 #ifdef AR934X_NFC_DEBUG_DATA
227 static void nfc_debug_data(const char *label
, void *data
, int len
)
229 print_hex_dump(KERN_WARNING
, label
, DUMP_PREFIX_OFFSET
, 16, 1,
233 static inline void nfc_debug_data(const char *label
, void *data
, int len
) {}
234 #endif /* AR934X_NFC_DEBUG_DATA */
236 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
);
238 static inline bool is_all_ff(u8
*buf
, int len
)
241 if (buf
[len
] != 0xff)
247 static inline void ar934x_nfc_wr(struct ar934x_nfc
*nfc
, unsigned reg
, u32 val
)
249 __raw_writel(val
, nfc
->base
+ reg
);
252 static inline u32
ar934x_nfc_rr(struct ar934x_nfc
*nfc
, unsigned reg
)
254 return __raw_readl(nfc
->base
+ reg
);
257 static inline struct ar934x_nfc
*mtd_to_ar934x_nfc(struct mtd_info
*mtd
)
259 struct nand_chip
*chip
= mtd_to_nand(mtd
);
261 return container_of(chip
, struct ar934x_nfc
, nand_chip
);
264 static struct mtd_info
*ar934x_nfc_to_mtd(struct ar934x_nfc
*nfc
)
266 return nand_to_mtd(&nfc
->nand_chip
);
269 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc
*nfc
)
271 return AR934X_NFC_USE_IRQ
;
274 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc
*nfc
, u32 cmd_reg
)
278 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CMD
, cmd_reg
);
280 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_CMD
);
283 static bool __ar934x_nfc_dev_ready(struct ar934x_nfc
*nfc
)
287 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
);
288 return (status
& 0xff) == 0xff;
291 static inline bool __ar934x_nfc_is_dma_ready(struct ar934x_nfc
*nfc
)
295 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
);
296 return (status
& AR934X_NFC_DMA_CTRL_DMA_READY
) != 0;
299 static int ar934x_nfc_wait_dev_ready(struct ar934x_nfc
*nfc
)
301 unsigned long timeout
;
303 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
);
305 if (__ar934x_nfc_dev_ready(nfc
))
307 } while time_before(jiffies
, timeout
);
309 nfc_dbg(nfc
, "timeout waiting for device ready, status:%08x int:%08x\n",
310 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_STATUS
),
311 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
));
315 static int ar934x_nfc_wait_dma_ready(struct ar934x_nfc
*nfc
)
317 unsigned long timeout
;
319 timeout
= jiffies
+ msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT
);
321 if (__ar934x_nfc_is_dma_ready(nfc
))
323 } while time_before(jiffies
, timeout
);
325 nfc_dbg(nfc
, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
326 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_DMA_CTRL
));
330 static int ar934x_nfc_wait_irq(struct ar934x_nfc
*nfc
)
335 timeout
= wait_event_timeout(nfc
->irq_waitq
,
336 (nfc
->irq_status
& AR934X_NFC_IRQ_MASK
) != 0,
337 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT
));
341 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
, 0);
342 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
344 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
347 "timeout waiting for interrupt, status:%08x\n",
356 static int ar934x_nfc_wait_done(struct ar934x_nfc
*nfc
)
360 if (ar934x_nfc_use_irq(nfc
))
361 ret
= ar934x_nfc_wait_irq(nfc
);
363 ret
= ar934x_nfc_wait_dev_ready(nfc
);
368 return ar934x_nfc_wait_dma_ready(nfc
);
371 static int ar934x_nfc_alloc_buf(struct ar934x_nfc
*nfc
, unsigned size
)
373 nfc
->buf
= dma_alloc_coherent(nfc
->parent
, size
,
374 &nfc
->buf_dma
, GFP_KERNEL
);
375 if (nfc
->buf
== NULL
) {
376 dev_err(nfc
->parent
, "no memory for DMA buffer\n");
380 nfc
->buf_size
= size
;
381 nfc_dbg(nfc
, "buf:%p size:%u\n", nfc
->buf
, nfc
->buf_size
);
386 static void ar934x_nfc_free_buf(struct ar934x_nfc
*nfc
)
388 dma_free_coherent(nfc
->parent
, nfc
->buf_size
, nfc
->buf
, nfc
->buf_dma
);
391 static void ar934x_nfc_get_addr(struct ar934x_nfc
*nfc
, int column
,
392 int page_addr
, u32
*addr0
, u32
*addr1
)
401 a0
= (page_addr
& 0xffff) << 16;
402 a1
= (page_addr
>> 16) & 0xf;
403 } else if (page_addr
!= -1) {
404 /* SEQIN, READ0, etc.. */
406 /* TODO: handle 16bit bus width */
407 if (nfc
->small_page
) {
409 a0
|= (page_addr
& 0xff) << 8;
410 a0
|= ((page_addr
>> 8) & 0xff) << 16;
411 a0
|= ((page_addr
>> 16) & 0xff) << 24;
413 a0
= column
& 0x0FFF;
414 a0
|= (page_addr
& 0xffff) << 16;
416 if (nfc
->addr_count0
> 4)
417 a1
= (page_addr
>> 16) & 0xf;
425 static void ar934x_nfc_send_cmd(struct ar934x_nfc
*nfc
, unsigned command
)
429 cmd_reg
= AR934X_NFC_CMD_INPUT_SEL_SIU
| AR934X_NFC_CMD_ADDR_SEL_0
|
430 AR934X_NFC_CMD_SEQ_1C
;
431 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
433 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
434 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
436 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
437 ar934x_nfc_wait_dev_ready(nfc
);
440 static int ar934x_nfc_do_rw_command(struct ar934x_nfc
*nfc
, int column
,
441 int page_addr
, int len
, u32 cmd_reg
,
442 u32 ctrl_reg
, bool write
)
452 if (WARN_ON(len
> nfc
->buf_size
))
453 dev_err(nfc
->parent
, "len=%d > buf_size=%d", len
,
457 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE
;
460 dma_ctrl
= AR934X_NFC_DMA_CTRL_DMA_DIR_READ
;
461 dir
= DMA_FROM_DEVICE
;
464 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
466 dma_ctrl
|= AR934X_NFC_DMA_CTRL_DMA_START
|
467 (AR934X_NFC_DMA_CTRL_DMA_BURST_3
<<
468 AR934X_NFC_DMA_CTRL_DMA_BURST_S
);
470 cmd_reg
|= AR934X_NFC_CMD_INPUT_SEL_DMA
| AR934X_NFC_CMD_ADDR_SEL_0
;
471 ctrl_reg
|= AR934X_NFC_CTRL_INT_EN
;
473 nfc_dbg(nfc
, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
474 (write
) ? "write" : "read",
475 addr0
, addr1
, len
, cmd_reg
, dma_ctrl
, ctrl_reg
);
478 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
479 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
480 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
481 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR
, nfc
->buf_dma
);
482 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_COUNT
, len
);
483 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DATA_SIZE
, len
);
484 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
485 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_CTRL
, dma_ctrl
);
486 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_CTRL
, nfc
->ecc_ctrl_reg
);
487 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ECC_OFFSET
, nfc
->ecc_offset_reg
);
489 if (ar934x_nfc_use_irq(nfc
)) {
490 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_MASK
,
491 AR934X_NFC_IRQ_MASK
);
493 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
496 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
497 err
= ar934x_nfc_wait_done(nfc
);
499 dev_dbg(nfc
->parent
, "%s operation stuck at page %d\n",
500 (write
) ? "write" : "read", page_addr
);
502 ar934x_nfc_restart(nfc
);
503 if (retries
++ < AR934X_NFC_DMA_RETRIES
)
506 dev_err(nfc
->parent
, "%s operation failed on page %d\n",
507 (write
) ? "write" : "read", page_addr
);
513 static int ar934x_nfc_send_readid(struct ar934x_nfc
*nfc
, unsigned command
)
518 nfc_dbg(nfc
, "readid, cmd:%02x\n", command
);
520 cmd_reg
= AR934X_NFC_CMD_SEQ_1C1AXR
;
521 cmd_reg
|= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
523 err
= ar934x_nfc_do_rw_command(nfc
, -1, -1, AR934X_NFC_ID_BUF_SIZE
,
524 cmd_reg
, nfc
->ctrl_reg
, false);
526 nfc_debug_data("[id] ", nfc
->buf
, AR934X_NFC_ID_BUF_SIZE
);
531 static int ar934x_nfc_send_read(struct ar934x_nfc
*nfc
, unsigned command
,
532 int column
, int page_addr
, int len
)
537 nfc_dbg(nfc
, "read, column=%d page=%d len=%d\n",
538 column
, page_addr
, len
);
540 cmd_reg
= (command
& AR934X_NFC_CMD_CMD0_M
) << AR934X_NFC_CMD_CMD0_S
;
542 if (nfc
->small_page
) {
543 cmd_reg
|= AR934X_NFC_CMD_SEQ_18
;
545 cmd_reg
|= NAND_CMD_READSTART
<< AR934X_NFC_CMD_CMD1_S
;
546 cmd_reg
|= AR934X_NFC_CMD_SEQ_1C5A1CXR
;
549 err
= ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
550 cmd_reg
, nfc
->ctrl_reg
, false);
552 nfc_debug_data("[data] ", nfc
->buf
, len
);
557 static void ar934x_nfc_send_erase(struct ar934x_nfc
*nfc
, unsigned command
,
558 int column
, int page_addr
)
564 ar934x_nfc_get_addr(nfc
, column
, page_addr
, &addr0
, &addr1
);
566 ctrl_reg
= nfc
->ctrl_reg
;
567 if (nfc
->small_page
) {
568 /* override number of address cycles for the erase command */
569 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M
<<
570 AR934X_NFC_CTRL_ADDR_CYCLE0_S
);
571 ctrl_reg
&= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M
<<
572 AR934X_NFC_CTRL_ADDR_CYCLE1_S
);
573 ctrl_reg
&= ~(AR934X_NFC_CTRL_SMALL_PAGE
);
574 ctrl_reg
|= (nfc
->addr_count0
+ 1) <<
575 AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
578 cmd_reg
= NAND_CMD_ERASE1
<< AR934X_NFC_CMD_CMD0_S
;
579 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
580 cmd_reg
|= AR934X_NFC_CMD_SEQ_ERASE
;
582 nfc_dbg(nfc
, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
583 page_addr
, addr0
, addr1
, cmd_reg
, ctrl_reg
);
585 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
586 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, ctrl_reg
);
587 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_0
, addr0
);
588 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_ADDR0_1
, addr1
);
590 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
591 ar934x_nfc_wait_dev_ready(nfc
);
594 static int ar934x_nfc_send_write(struct ar934x_nfc
*nfc
, unsigned command
,
595 int column
, int page_addr
, int len
)
599 nfc_dbg(nfc
, "write, column=%d page=%d len=%d\n",
600 column
, page_addr
, len
);
602 nfc_debug_data("[data] ", nfc
->buf
, len
);
604 cmd_reg
= NAND_CMD_SEQIN
<< AR934X_NFC_CMD_CMD0_S
;
605 cmd_reg
|= command
<< AR934X_NFC_CMD_CMD1_S
;
606 cmd_reg
|= AR934X_NFC_CMD_SEQ_12
;
608 return ar934x_nfc_do_rw_command(nfc
, column
, page_addr
, len
,
609 cmd_reg
, nfc
->ctrl_reg
, true);
612 static void ar934x_nfc_read_status(struct ar934x_nfc
*nfc
)
617 cmd_reg
= NAND_CMD_STATUS
<< AR934X_NFC_CMD_CMD0_S
;
618 cmd_reg
|= AR934X_NFC_CMD_SEQ_S
;
620 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
621 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
623 ar934x_nfc_write_cmd_reg(nfc
, cmd_reg
);
624 ar934x_nfc_wait_dev_ready(nfc
);
626 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_READ_STATUS
);
628 nfc_dbg(nfc
, "read status, cmd:%08x status:%02x\n",
629 cmd_reg
, (status
& 0xff));
632 nfc
->buf
[0 ^ 3] = status
;
634 nfc
->buf
[0] = status
;
637 static void ar934x_nfc_cmdfunc(struct nand_chip
*nand
, unsigned int command
,
638 int column
, int page_addr
)
640 struct mtd_info
*mtd
= nand_to_mtd(nand
);
641 struct ar934x_nfc
*nfc
= nand
->priv
;
643 nfc
->read_id
= false;
644 if (command
!= NAND_CMD_PAGEPROG
)
649 ar934x_nfc_send_cmd(nfc
, command
);
652 case NAND_CMD_READID
:
654 ar934x_nfc_send_readid(nfc
, command
);
659 if (nfc
->small_page
) {
660 ar934x_nfc_send_read(nfc
, command
, column
, page_addr
,
661 mtd
->writesize
+ mtd
->oobsize
);
663 ar934x_nfc_send_read(nfc
, command
, 0, page_addr
,
664 mtd
->writesize
+ mtd
->oobsize
);
665 nfc
->buf_index
= column
;
666 nfc
->rndout_page_addr
= page_addr
;
667 nfc
->rndout_read_cmd
= command
;
671 case NAND_CMD_READOOB
:
673 ar934x_nfc_send_read(nfc
, NAND_CMD_READOOB
,
677 ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
,
678 mtd
->writesize
, page_addr
,
682 case NAND_CMD_RNDOUT
:
683 if (WARN_ON(nfc
->small_page
))
686 /* emulate subpage read */
687 ar934x_nfc_send_read(nfc
, nfc
->rndout_read_cmd
, 0,
688 nfc
->rndout_page_addr
,
689 mtd
->writesize
+ mtd
->oobsize
);
690 nfc
->buf_index
= column
;
693 case NAND_CMD_ERASE1
:
694 nfc
->erase1_page_addr
= page_addr
;
697 case NAND_CMD_ERASE2
:
698 ar934x_nfc_send_erase(nfc
, command
, -1, nfc
->erase1_page_addr
);
701 case NAND_CMD_STATUS
:
702 ar934x_nfc_read_status(nfc
);
706 if (nfc
->small_page
) {
707 /* output read command */
708 if (column
>= mtd
->writesize
) {
709 column
-= mtd
->writesize
;
710 nfc
->seqin_read_cmd
= NAND_CMD_READOOB
;
711 } else if (column
< 256) {
712 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
715 nfc
->seqin_read_cmd
= NAND_CMD_READ1
;
718 nfc
->seqin_read_cmd
= NAND_CMD_READ0
;
720 nfc
->seqin_column
= column
;
721 nfc
->seqin_page_addr
= page_addr
;
724 case NAND_CMD_PAGEPROG
:
725 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
726 if (nand
->ecc
.engine_type
== NAND_ECC_ENGINE_TYPE_ON_HOST
) {
728 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
730 /* the data is already written */
735 ar934x_nfc_send_cmd(nfc
, nfc
->seqin_read_cmd
);
737 ar934x_nfc_send_write(nfc
, command
, nfc
->seqin_column
,
738 nfc
->seqin_page_addr
,
744 "unsupported command: %x, column:%d page_addr=%d\n",
745 command
, column
, page_addr
);
750 static int ar934x_nfc_dev_ready(struct nand_chip
*chip
)
752 struct ar934x_nfc
*nfc
= chip
->priv
;
754 return __ar934x_nfc_dev_ready(nfc
);
757 static u8
ar934x_nfc_read_byte(struct nand_chip
*chip
)
759 struct ar934x_nfc
*nfc
= chip
->priv
;
762 WARN_ON(nfc
->buf_index
>= nfc
->buf_size
);
764 if (nfc
->swap_dma
|| nfc
->read_id
)
765 data
= nfc
->buf
[nfc
->buf_index
^ 3];
767 data
= nfc
->buf
[nfc
->buf_index
];
774 static void ar934x_nfc_write_buf(struct nand_chip
*chip
, const u8
*buf
, int len
)
776 struct ar934x_nfc
*nfc
= chip
->priv
;
779 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
782 for (i
= 0; i
< len
; i
++) {
783 nfc
->buf
[nfc
->buf_index
^ 3] = buf
[i
];
787 for (i
= 0; i
< len
; i
++) {
788 nfc
->buf
[nfc
->buf_index
] = buf
[i
];
794 static void ar934x_nfc_read_buf(struct nand_chip
*chip
, u8
*buf
, int len
)
796 struct ar934x_nfc
*nfc
= chip
->priv
;
800 WARN_ON(nfc
->buf_index
+ len
> nfc
->buf_size
);
802 buf_index
= nfc
->buf_index
;
804 if (nfc
->swap_dma
|| nfc
->read_id
) {
805 for (i
= 0; i
< len
; i
++) {
806 buf
[i
] = nfc
->buf
[buf_index
^ 3];
810 for (i
= 0; i
< len
; i
++) {
811 buf
[i
] = nfc
->buf
[buf_index
];
816 nfc
->buf_index
= buf_index
;
819 static inline void ar934x_nfc_enable_hwecc(struct ar934x_nfc
*nfc
)
821 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_ECC_EN
;
822 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
825 static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc
*nfc
)
827 nfc
->ctrl_reg
&= ~AR934X_NFC_CTRL_ECC_EN
;
828 nfc
->ctrl_reg
|= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
831 static int ar934x_nfc_read_oob(struct nand_chip
*chip
,
834 struct ar934x_nfc
*nfc
= chip
->priv
;
835 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
838 nfc_dbg(nfc
, "read_oob: page:%d\n", page
);
840 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
, page
,
845 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
850 static int ar934x_nfc_write_oob(struct nand_chip
*chip
,
853 struct ar934x_nfc
*nfc
= chip
->priv
;
854 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
855 nfc_dbg(nfc
, "write_oob: page:%d\n", page
);
857 memcpy(nfc
->buf
, chip
->oob_poi
, mtd
->oobsize
);
859 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, mtd
->writesize
,
863 static int ar934x_nfc_read_page_raw(
864 struct nand_chip
*chip
, u8
*buf
,
865 int oob_required
, int page
)
867 struct ar934x_nfc
*nfc
= chip
->priv
;
868 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
872 nfc_dbg(nfc
, "read_page_raw: page:%d oob:%d\n", page
, oob_required
);
874 len
= mtd
->writesize
;
878 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
, len
);
882 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
885 memcpy(chip
->oob_poi
, &nfc
->buf
[mtd
->writesize
], mtd
->oobsize
);
890 static int ar934x_nfc_read_page(struct nand_chip
*chip
,
891 u8
*buf
, int oob_required
, int page
)
893 struct ar934x_nfc
*nfc
= chip
->priv
;
894 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
896 int max_bitflips
= 0;
901 nfc_dbg(nfc
, "read_page: page:%d oob:%d\n", page
, oob_required
);
903 ar934x_nfc_enable_hwecc(nfc
);
904 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, 0, page
,
906 ar934x_nfc_disable_hwecc(nfc
);
911 /* TODO: optimize to avoid memcpy */
912 memcpy(buf
, nfc
->buf
, mtd
->writesize
);
914 /* read the ECC status */
915 ecc_ctrl
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_ECC_CTRL
);
916 ecc_failed
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_UNCORRECT
;
917 ecc_corrected
= ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_CORRECT
;
919 if (oob_required
|| ecc_failed
) {
920 err
= ar934x_nfc_send_read(nfc
, NAND_CMD_READ0
, mtd
->writesize
,
926 memcpy(chip
->oob_poi
, nfc
->buf
, mtd
->oobsize
);
931 * The hardware ECC engine reports uncorrectable errors
932 * on empty pages. Check the ECC bytes and the data. If
933 * both contains 0xff bytes only, dont report a failure.
935 * TODO: prebuild a buffer with 0xff bytes and use memcmp
936 * for better performance?
938 if (!is_all_ff(&nfc
->buf
[nfc
->ecc_oob_pos
], chip
->ecc
.total
) ||
939 !is_all_ff(buf
, mtd
->writesize
))
940 mtd
->ecc_stats
.failed
++;
941 } else if (ecc_corrected
) {
943 * The hardware does not report the exact count of the
944 * corrected bitflips, use assumptions based on the
947 if (ecc_ctrl
& AR934X_NFC_ECC_CTRL_ERR_OVER
) {
949 * The number of corrected bitflips exceeds the
950 * threshold. Assume the maximum.
952 max_bitflips
= chip
->ecc
.strength
* chip
->ecc
.steps
;
954 max_bitflips
= nfc
->ecc_thres
* chip
->ecc
.steps
;
957 mtd
->ecc_stats
.corrected
+= max_bitflips
;
963 static int ar934x_nfc_write_page_raw(
964 struct nand_chip
*chip
, const u8
*buf
,
965 int oob_required
, int page
)
967 struct ar934x_nfc
*nfc
= chip
->priv
;
968 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
971 nfc_dbg(nfc
, "write_page_raw: page:%d oob:%d\n", page
, oob_required
);
973 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
974 len
= mtd
->writesize
;
977 memcpy(&nfc
->buf
[mtd
->writesize
], chip
->oob_poi
, mtd
->oobsize
);
981 return ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
, len
);
984 static int ar934x_nfc_write_page(struct nand_chip
*chip
,
985 const u8
*buf
, int oob_required
, int page
)
987 struct ar934x_nfc
*nfc
= chip
->priv
;
988 struct mtd_info
*mtd
= ar934x_nfc_to_mtd(nfc
);
991 nfc_dbg(nfc
, "write_page: page:%d oob:%d\n", page
, oob_required
);
993 /* write OOB first */
995 !is_all_ff(chip
->oob_poi
, mtd
->oobsize
)) {
996 err
= ar934x_nfc_write_oob(chip
, page
);
1001 /* TODO: optimize to avoid memcopy */
1002 memcpy(nfc
->buf
, buf
, mtd
->writesize
);
1004 ar934x_nfc_enable_hwecc(nfc
);
1005 err
= ar934x_nfc_send_write(nfc
, NAND_CMD_PAGEPROG
, 0, page
,
1007 ar934x_nfc_disable_hwecc(nfc
);
1012 static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc
*nfc
)
1016 err
= reset_control_assert(nfc
->rst
);
1021 static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc
*nfc
)
1025 err
= reset_control_deassert(nfc
->rst
);
1030 static int ar934x_nfc_hw_init(struct ar934x_nfc
*nfc
)
1032 ar934x_nfc_hw_reset_assert(nfc
);
1033 ar934x_nfc_hw_reset_deassert(nfc
);
1036 * TODO: make it configurable via platform data or DT
1038 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIME_SEQ
,
1039 AR934X_NFC_TIME_SEQ_DEFAULT
);
1040 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_ASYN
,
1041 AR934X_NFC_TIMINGS_ASYN_DEFAULT
);
1042 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_TIMINGS_SYN
,
1043 AR934X_NFC_TIMINGS_SYN_DEFAULT
);
1045 /* disable WP on all chips, and select chip 0 */
1046 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_MEM_CTRL
, 0xff00);
1048 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_DMA_ADDR_OFFS
, 0);
1050 /* initialize Control register */
1051 nfc
->ctrl_reg
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1052 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1054 if (nfc
->small_page
) {
1055 /* Setup generic sequence register for small page reads. */
1056 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_GEN_SEQ_CTRL
,
1057 AR934X_NFC_GENSEQ_SMALL_PAGE_READ
);
1063 static void ar934x_nfc_restart(struct ar934x_nfc
*nfc
)
1067 ctrl_reg
= nfc
->ctrl_reg
;
1068 ar934x_nfc_hw_init(nfc
);
1069 nfc
->ctrl_reg
= ctrl_reg
;
1071 ar934x_nfc_send_cmd(nfc
, NAND_CMD_RESET
);
1074 static irqreturn_t
ar934x_nfc_irq_handler(int irq
, void *data
)
1076 struct ar934x_nfc
*nfc
= data
;
1079 status
= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1081 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_INT_STATUS
, 0);
1083 ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_STATUS
);
1085 status
&= ar934x_nfc_rr(nfc
, AR934X_NFC_REG_INT_MASK
);
1087 nfc_dbg(nfc
, "got IRQ, status:%08x\n", status
);
1089 nfc
->irq_status
= status
;
1090 nfc
->spurious_irq_expected
= true;
1091 wake_up(&nfc
->irq_waitq
);
1093 if (nfc
->spurious_irq_expected
)
1094 nfc
->spurious_irq_expected
= false;
1096 dev_warn(nfc
->parent
, "spurious interrupt\n");
1102 static int ar934x_nfc_init_tail(struct mtd_info
*mtd
)
1104 struct ar934x_nfc
*nfc
= mtd_to_ar934x_nfc(mtd
);
1105 struct nand_chip
*chip
= &nfc
->nand_chip
;
1106 u64 chipsize
= nanddev_target_size(&chip
->base
);
1111 switch (mtd
->oobsize
) {
1115 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_SPARE_SIZE
, mtd
->oobsize
);
1119 dev_err(nfc
->parent
, "unsupported OOB size: %d bytes\n",
1124 ctrl
= AR934X_NFC_CTRL_CUSTOM_SIZE_EN
;
1126 switch (mtd
->erasesize
/ mtd
->writesize
) {
1128 t
= AR934X_NFC_CTRL_BLOCK_SIZE_32
;
1132 t
= AR934X_NFC_CTRL_BLOCK_SIZE_64
;
1136 t
= AR934X_NFC_CTRL_BLOCK_SIZE_128
;
1140 t
= AR934X_NFC_CTRL_BLOCK_SIZE_256
;
1144 dev_err(nfc
->parent
, "unsupported block size: %u\n",
1145 mtd
->erasesize
/ mtd
->writesize
);
1149 ctrl
|= t
<< AR934X_NFC_CTRL_BLOCK_SIZE_S
;
1151 switch (mtd
->writesize
) {
1153 nfc
->small_page
= 1;
1154 t
= AR934X_NFC_CTRL_PAGE_SIZE_256
;
1158 nfc
->small_page
= 1;
1159 t
= AR934X_NFC_CTRL_PAGE_SIZE_512
;
1163 t
= AR934X_NFC_CTRL_PAGE_SIZE_1024
;
1167 t
= AR934X_NFC_CTRL_PAGE_SIZE_2048
;
1171 t
= AR934X_NFC_CTRL_PAGE_SIZE_4096
;
1175 t
= AR934X_NFC_CTRL_PAGE_SIZE_8192
;
1179 t
= AR934X_NFC_CTRL_PAGE_SIZE_16384
;
1183 dev_err(nfc
->parent
, "unsupported write size: %d bytes\n",
1188 ctrl
|= t
<< AR934X_NFC_CTRL_PAGE_SIZE_S
;
1190 if (nfc
->small_page
) {
1191 ctrl
|= AR934X_NFC_CTRL_SMALL_PAGE
;
1193 if (chipsize
> (32 << 20)) {
1194 nfc
->addr_count0
= 4;
1195 nfc
->addr_count1
= 3;
1196 } else if (chipsize
> (2 << 16)) {
1197 nfc
->addr_count0
= 3;
1198 nfc
->addr_count1
= 2;
1200 nfc
->addr_count0
= 2;
1201 nfc
->addr_count1
= 1;
1204 if (chipsize
> (128 << 20)) {
1205 nfc
->addr_count0
= 5;
1206 nfc
->addr_count1
= 3;
1207 } else if (chipsize
> (8 << 16)) {
1208 nfc
->addr_count0
= 4;
1209 nfc
->addr_count1
= 2;
1211 nfc
->addr_count0
= 3;
1212 nfc
->addr_count1
= 1;
1216 ctrl
|= nfc
->addr_count0
<< AR934X_NFC_CTRL_ADDR_CYCLE0_S
;
1217 ctrl
|= nfc
->addr_count1
<< AR934X_NFC_CTRL_ADDR_CYCLE1_S
;
1219 nfc
->ctrl_reg
= ctrl
;
1220 ar934x_nfc_wr(nfc
, AR934X_NFC_REG_CTRL
, nfc
->ctrl_reg
);
1222 ar934x_nfc_free_buf(nfc
);
1223 err
= ar934x_nfc_alloc_buf(nfc
, mtd
->writesize
+ mtd
->oobsize
);
1228 static int ar934x_nfc_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1229 struct mtd_oob_region
*oobregion
)
1234 oobregion
->offset
= 20;
1235 oobregion
->length
= 28;
1240 static int ar934x_nfc_ooblayout_free(struct mtd_info
*mtd
, int section
,
1241 struct mtd_oob_region
*oobregion
)
1245 oobregion
->offset
= 4;
1246 oobregion
->length
= 16;
1249 oobregion
->offset
= 48;
1250 oobregion
->length
= 16;
1257 static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops
= {
1258 .ecc
= ar934x_nfc_ooblayout_ecc
,
1259 .free
= ar934x_nfc_ooblayout_free
,
1262 static int ar934x_nfc_setup_hwecc(struct ar934x_nfc
*nfc
)
1264 struct nand_chip
*nand
= &nfc
->nand_chip
;
1265 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1268 struct mtd_oob_region oobregion
;
1270 switch (mtd
->writesize
) {
1273 * Writing a subpage separately is not supported, because
1274 * the controller only does ECC on full-page accesses.
1277 nand
->ecc
.size
= 512;
1278 nand
->ecc
.bytes
= 7;
1279 nand
->ecc
.strength
= 4;
1280 mtd_set_ooblayout(mtd
, &ar934x_nfc_ecclayout_ops
);
1284 dev_err(nfc
->parent
,
1285 "hardware ECC is not available for %d byte pages\n",
1290 BUG_ON(!mtd
->ooblayout
->ecc
);
1292 switch (nand
->ecc
.strength
) {
1294 ecc_cap
= AR934X_NFC_ECC_CTRL_ECC_CAP_4
;
1299 dev_err(nfc
->parent
, "unsupported ECC strength %u\n",
1300 nand
->ecc
.strength
);
1304 nfc
->ecc_thres
= ecc_thres
;
1305 mtd
->ooblayout
->ecc(mtd
, 0, &oobregion
);
1306 nfc
->ecc_oob_pos
= oobregion
.offset
;
1308 nfc
->ecc_ctrl_reg
= ecc_cap
<< AR934X_NFC_ECC_CTRL_ECC_CAP_S
;
1309 nfc
->ecc_ctrl_reg
|= ecc_thres
<< AR934X_NFC_ECC_CTRL_ERR_THRES_S
;
1311 nfc
->ecc_offset_reg
= mtd
->writesize
+ nfc
->ecc_oob_pos
;
1313 nand
->ecc
.read_page
= ar934x_nfc_read_page
;
1314 nand
->ecc
.read_page_raw
= ar934x_nfc_read_page_raw
;
1315 nand
->ecc
.write_page
= ar934x_nfc_write_page
;
1316 nand
->ecc
.write_page_raw
= ar934x_nfc_write_page_raw
;
1317 nand
->ecc
.read_oob
= ar934x_nfc_read_oob
;
1318 nand
->ecc
.write_oob
= ar934x_nfc_write_oob
;
1323 static int ar934x_nfc_attach_chip(struct nand_chip
*nand
)
1325 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1326 struct ar934x_nfc
*nfc
= nand_get_controller_data(nand
);
1327 struct device
*dev
= mtd
->dev
.parent
;
1330 ret
= ar934x_nfc_init_tail(mtd
);
1334 if (mtd
->writesize
== 2048)
1335 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
1337 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1338 if (nand
->ecc
.engine_type
== NAND_ECC_ENGINE_TYPE_ON_HOST
) {
1340 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
1342 ret
= ar934x_nfc_setup_hwecc(nfc
);
1345 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1346 } else if (nand
->ecc
.engine_type
!= NAND_ECC_ENGINE_TYPE_SOFT
) {
1347 dev_err(dev
, "unknown ECC mode %d\n", nand
->ecc
.engine_type
);
1349 } else if (nand
->ecc
.mode
!= NAND_ECC_SOFT
) {
1350 dev_err(dev
, "unknown ECC mode %d\n", nand
->ecc
.mode
);
1353 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1354 } else if ((nand
->ecc
.algo
!= NAND_ECC_ALGO_BCH
) &&
1355 (nand
->ecc
.algo
!= NAND_ECC_ALGO_HAMMING
)) {
1357 } else if ((nand
->ecc
.algo
!= NAND_ECC_BCH
) &&
1358 (nand
->ecc
.algo
!= NAND_ECC_HAMMING
)) {
1360 dev_err(dev
, "unknown software ECC algo %d\n", nand
->ecc
.algo
);
1367 static u64 ar934x_nfc_dma_mask
= DMA_BIT_MASK(32);
1369 static void ar934x_nfc_cmd_ctrl(struct nand_chip
*chip
, int dat
,
1372 WARN_ON(dat
!= NAND_CMD_NONE
);
1375 static const struct nand_controller_ops ar934x_nfc_controller_ops
= {
1376 .attach_chip
= ar934x_nfc_attach_chip
,
1379 static int ar934x_nfc_probe(struct platform_device
*pdev
)
1381 struct ar934x_nfc
*nfc
;
1382 struct resource
*res
;
1383 struct mtd_info
*mtd
;
1384 struct nand_chip
*nand
;
1387 pdev
->dev
.dma_mask
= &ar934x_nfc_dma_mask
;
1388 pdev
->dev
.coherent_dma_mask
= DMA_BIT_MASK(32);
1390 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1392 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
1396 nfc
= devm_kzalloc(&pdev
->dev
, sizeof(struct ar934x_nfc
), GFP_KERNEL
);
1398 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
1402 nfc
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1403 if (IS_ERR(nfc
->base
)) {
1404 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
1405 return PTR_ERR(nfc
->base
);
1408 nfc
->irq
= platform_get_irq(pdev
, 0);
1410 dev_err(&pdev
->dev
, "no IRQ resource specified\n");
1414 init_waitqueue_head(&nfc
->irq_waitq
);
1415 ret
= devm_request_irq(&pdev
->dev
, nfc
->irq
, ar934x_nfc_irq_handler
,
1416 0, AR934X_NFC_DRIVER_NAME
, nfc
);
1418 dev_err(&pdev
->dev
, "devm_request_irq failed, err:%d\n", ret
);
1422 nfc
->rst
= devm_reset_control_get(&pdev
->dev
, "nand");
1423 if (IS_ERR(nfc
->rst
)) {
1424 dev_err(&pdev
->dev
, "Failed to get reset\n");
1425 return PTR_ERR(nfc
->rst
);
1428 nfc
->parent
= &pdev
->dev
;
1429 nfc
->swap_dma
= of_property_read_bool(pdev
->dev
.of_node
,
1430 "qca,nand-swap-dma");
1432 nand
= &nfc
->nand_chip
;
1433 mtd
= nand_to_mtd(nand
);
1435 mtd
->owner
= THIS_MODULE
;
1436 mtd
->dev
.parent
= &pdev
->dev
;
1437 mtd
->name
= AR934X_NFC_DRIVER_NAME
;
1439 nand_set_controller_data(nand
, nfc
);
1440 nand_set_flash_node(nand
, pdev
->dev
.of_node
);
1441 nand
->legacy
.chip_delay
= 25;
1442 nand
->legacy
.dev_ready
= ar934x_nfc_dev_ready
;
1443 nand
->legacy
.cmdfunc
= ar934x_nfc_cmdfunc
;
1444 nand
->legacy
.cmd_ctrl
= ar934x_nfc_cmd_ctrl
; /* dummy */
1445 nand
->legacy
.read_byte
= ar934x_nfc_read_byte
;
1446 nand
->legacy
.write_buf
= ar934x_nfc_write_buf
;
1447 nand
->legacy
.read_buf
= ar934x_nfc_read_buf
;
1448 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1449 nand
->ecc
.engine_type
= NAND_ECC_ENGINE_TYPE_ON_HOST
; /* default */
1451 nand
->ecc
.mode
= NAND_ECC_HW
; /* default */
1454 platform_set_drvdata(pdev
, nfc
);
1456 ret
= ar934x_nfc_alloc_buf(nfc
, AR934X_NFC_ID_BUF_SIZE
);
1460 ret
= ar934x_nfc_hw_init(nfc
);
1462 dev_err(&pdev
->dev
, "hardware init failed, err:%d\n", ret
);
1466 nand
->legacy
.dummy_controller
.ops
= &ar934x_nfc_controller_ops
;
1467 ret
= nand_scan(nand
, 1);
1469 dev_err(&pdev
->dev
, "nand_scan failed, err:%d\n", ret
);
1473 ret
= mtd_device_register(mtd
, NULL
, 0);
1475 dev_err(&pdev
->dev
, "unable to register mtd, err:%d\n", ret
);
1482 ar934x_nfc_free_buf(nfc
);
1486 static int ar934x_nfc_remove(struct platform_device
*pdev
)
1488 struct ar934x_nfc
*nfc
;
1490 nfc
= platform_get_drvdata(pdev
);
1492 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
1493 mtd_device_unregister(nand_to_mtd(&nfc
->nand_chip
));
1494 nand_cleanup(&nfc
->nand_chip
);
1496 nand_release(&nfc
->nand_chip
);
1498 ar934x_nfc_free_buf(nfc
);
1504 static const struct of_device_id ar934x_nfc_match
[] = {
1505 { .compatible
= "qca," AR934X_NFC_DRIVER_NAME
},
1509 MODULE_DEVICE_TABLE(of
, ar934x_nfc_match
);
1511 static struct platform_driver ar934x_nfc_driver
= {
1512 .probe
= ar934x_nfc_probe
,
1513 .remove
= ar934x_nfc_remove
,
1515 .name
= AR934X_NFC_DRIVER_NAME
,
1516 .owner
= THIS_MODULE
,
1517 .of_match_table
= ar934x_nfc_match
,
1521 module_platform_driver(ar934x_nfc_driver
);
1523 MODULE_LICENSE("GPL v2");
1524 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1525 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1526 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME
);