1 --- a/arch/mips/pci/pci-ar71xx.c
2 +++ b/arch/mips/pci/pci-ar71xx.c
4 struct ar71xx_pci_controller {
5 struct device_node *np;
6 void __iomem *cfg_base;
8 struct pci_controller pci_ctrl;
9 struct resource io_res;
10 struct resource mem_res;
11 - struct irq_domain *domain;
14 /* Byte lane enable bits */
15 @@ -230,104 +228,6 @@ static struct pci_ops ar71xx_pci_ops = {
16 .write = ar71xx_pci_write_config,
19 -static void ar71xx_pci_irq_handler(struct irq_desc *desc)
21 - void __iomem *base = ath79_reset_base;
22 - struct irq_chip *chip = irq_desc_get_chip(desc);
23 - struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
26 - chained_irq_enter(chip, desc);
27 - pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
28 - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
30 - if (pending & AR71XX_PCI_INT_DEV0)
31 - generic_handle_irq(irq_linear_revmap(apc->domain, 1));
33 - else if (pending & AR71XX_PCI_INT_DEV1)
34 - generic_handle_irq(irq_linear_revmap(apc->domain, 2));
36 - else if (pending & AR71XX_PCI_INT_DEV2)
37 - generic_handle_irq(irq_linear_revmap(apc->domain, 3));
39 - else if (pending & AR71XX_PCI_INT_CORE)
40 - generic_handle_irq(irq_linear_revmap(apc->domain, 4));
43 - spurious_interrupt();
44 - chained_irq_exit(chip, desc);
47 -static void ar71xx_pci_irq_unmask(struct irq_data *d)
49 - struct ar71xx_pci_controller *apc;
51 - void __iomem *base = ath79_reset_base;
54 - apc = irq_data_get_irq_chip_data(d);
55 - irq = irq_linear_revmap(apc->domain, d->irq);
57 - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
58 - __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
61 - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
64 -static void ar71xx_pci_irq_mask(struct irq_data *d)
66 - struct ar71xx_pci_controller *apc;
68 - void __iomem *base = ath79_reset_base;
71 - apc = irq_data_get_irq_chip_data(d);
72 - irq = irq_linear_revmap(apc->domain, d->irq);
74 - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
75 - __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
78 - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
81 -static struct irq_chip ar71xx_pci_irq_chip = {
82 - .name = "AR71XX PCI",
83 - .irq_mask = ar71xx_pci_irq_mask,
84 - .irq_unmask = ar71xx_pci_irq_unmask,
85 - .irq_mask_ack = ar71xx_pci_irq_mask,
88 -static int ar71xx_pci_irq_map(struct irq_domain *d,
89 - unsigned int irq, irq_hw_number_t hw)
91 - struct ar71xx_pci_controller *apc = d->host_data;
93 - irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
94 - irq_set_chip_data(irq, apc);
99 -static const struct irq_domain_ops ar71xx_pci_domain_ops = {
100 - .xlate = irq_domain_xlate_onecell,
101 - .map = ar71xx_pci_irq_map,
104 -static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
106 - void __iomem *base = ath79_reset_base;
108 - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
109 - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
111 - apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
112 - &ar71xx_pci_domain_ops, apc);
113 - irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
117 static void ar71xx_pci_reset(void)
119 ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
120 @@ -361,10 +261,6 @@ static int ar71xx_pci_probe(struct platf
121 if (IS_ERR(apc->cfg_base))
122 return PTR_ERR(apc->cfg_base);
124 - apc->irq = platform_get_irq(pdev, 0);
130 /* setup COMMAND register */
131 @@ -375,8 +271,6 @@ static int ar71xx_pci_probe(struct platf
132 /* clear bus errors */
133 ar71xx_pci_check_error(apc, 1);
135 - ar71xx_pci_irq_init(apc);
137 apc->np = pdev->dev.of_node;
138 apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
139 apc->pci_ctrl.mem_resource = &apc->mem_res;