target/linux/ath79/patches-5.10/0053-mtd-spi-nor-use-4-bit-BP-for-large-Macronix-flash.patch

   1 From 59f88b8d4447be809d0b5e7a283290d06848d3bc Mon Sep 17 00:00:00 2001
   2 From: David Bauer <mail@david-bauer.net>
   3 Date: Sun, 25 Oct 2020 01:14:22 +0200
   4 Subject: [PATCH 2/2] mtd: spi-nor: use 4 bit BP for large Macronix flash
   5
   6 Macronix SPI-NOR chips with 128 or more 64k blocks have 4 block
   7 protection bits in their status register. Add the corresponding
   8 flag in order to clear these bits when unloking the flash.
   9
  10 Otherwise, the flash might not be writable depending on the state the
  11 bootloader left the flash in.
  12
  13 Fixes commit 62593cf40b23 ("mtd: spi-nor: refactor block protection functions")
  14
  15 Signed-off-by: David Bauer <mail@david-bauer.net>
  16 ---
  17  drivers/mtd/spi-nor/macronix.c | 31 ++++++++++++++++++-------------
  18  1 file changed, 18 insertions(+), 13 deletions(-)
  19
  20 --- a/drivers/mtd/spi-nor/macronix.c
  21 +++ b/drivers/mtd/spi-nor/macronix.c
  22 @@ -50,8 +50,8 @@ static const struct flash_info macronix_
  23         { "mx25u4035",   INFO(0xc22533, 0, 64 * 1024,   8, SECT_4K) },
  24         { "mx25u8035",   INFO(0xc22534, 0, 64 * 1024,  16, SECT_4K) },
  25         { "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
  26 -       { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K) },
  27 -       { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
  28 +       { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_4BIT_BP) },
  29 +       { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, SPI_NOR_4BIT_BP) },
  30         { "mx25r1635f",  INFO(0xc22815, 0, 64 * 1024,  32,
  31                               SECT_4K | SPI_NOR_DUAL_READ |
  32                               SPI_NOR_QUAD_READ) },
  33 @@ -60,36 +60,41 @@ static const struct flash_info macronix_
  34                               SPI_NOR_QUAD_READ) },
  35         { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
  36                               SECT_4K | SPI_NOR_DUAL_READ |
  37 -                             SPI_NOR_QUAD_READ) },
  38 +                             SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
  39         { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
  40 -                             SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
  41 +                             SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  42 +                             SPI_NOR_4BIT_BP)
  43                 .fixups = &mx25l25635_fixups },
  44         { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
  45 -                             SECT_4K | SPI_NOR_4B_OPCODES) },
  46 +                             SECT_4K | SPI_NOR_4B_OPCODES |
  47 +                             SPI_NOR_4BIT_BP) },
  48         { "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
  49                               SECT_4K | SPI_NOR_DUAL_READ |
  50 -                             SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  51 +                             SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
  52 +                             SPI_NOR_4BIT_BP) },
  53         { "mx25v8035f",  INFO(0xc22314, 0, 64 * 1024,  16,
  54                               SECT_4K | SPI_NOR_DUAL_READ |
  55                               SPI_NOR_QUAD_READ) },
  56 -       { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
  57 +       { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, SPI_NOR_4BIT_BP) },
  58         { "mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
  59                               SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  60 -                             SPI_NOR_4B_OPCODES) },
  61 +                             SPI_NOR_4B_OPCODES | SPI_NOR_4BIT_BP) },
  62         { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024,
  63                               SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  64 -                             SPI_NOR_4B_OPCODES) },
  65 +                             SPI_NOR_4B_OPCODES | SPI_NOR_4BIT_BP) },
  66         { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
  67                               SECT_4K | SPI_NOR_DUAL_READ |
  68 -                             SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  69 +                             SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
  70 +                             SPI_NOR_4BIT_BP) },
  71         { "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048,
  72                               SECT_4K | SPI_NOR_DUAL_READ |
  73 -                             SPI_NOR_QUAD_READ) },
  74 +                             SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
  75         { "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
  76 -                             SPI_NOR_QUAD_READ) },
  77 +                             SPI_NOR_QUAD_READ | SPI_NOR_4BIT_BP) },
  78         { "mx66u2g45g",  INFO(0xc2253c, 0, 64 * 1024, 4096,
  79                               SECT_4K | SPI_NOR_DUAL_READ |
  80 -                             SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
  81 +                             SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
  82 +                             SPI_NOR_4BIT_BP) },
  83  };
  84
  85  static void macronix_default_init(struct spi_nor *nor)