target/linux/ath79/patches-5.4/450-fix-block-protection-clearing.patch

   1 From: Nick Hainke <vincent@systemli.org>
   2 Date: Sun, 25 Oct 2020 00:52:47 +0200
   3 Subject: [PATCH] ath79: fix block protection clearing
   4
   5 The block protection bits of macronix do not match the implementation.
   6 The chip has 3 BP bits. Bit 5 is actually the third BP but here the
   7 5th bit is SR_TB. Therefore the patch adds SR_TB to the mask. In the
   8 4.19er kernel the whole register was simply set to 0.
   9
  10 The wrong implementation did not remove the block protection. This led
  11 to jffs2 errors in the form of:
  12 "jffs2: Newly-erased block contained word 0x19852003 at offset 0x..."
  13 This caused inconsistent memory and other errors.
  14
  15 Suggested-by: David Bauer <mail@david-bauer.net>
  16 Signed-off-by: Nick Hainke <vincent@systemli.org>
  17
  18 --- a/drivers/mtd/spi-nor/spi-nor.c
  19 +++ b/drivers/mtd/spi-nor/spi-nor.c
  20 @@ -1985,7 +1985,7 @@ static int sr2_bit7_quad_enable(struct s
  21  static int spi_nor_clear_sr_bp(struct spi_nor *nor)
  22  {
  23         int ret;
  24 -       u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  25 +       u8 mask = SR_TB | SR_BP2 | SR_BP1 | SR_BP0;
  26
  27         if (nor->flags & SNOR_F_HAS_4BIT_BP)
  28                 mask |= SR_BP3;