target/linux/atheros/files/arch/mips/atheros/ar5315/irq.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/string.h>
  20 #include <linux/kernel.h>
  21 #include <linux/reboot.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bitops.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/irq_cpu.h>
  26 #include <asm/io.h>
  27
  28 #include <ar531x.h>
  29 #include <gpio.h>
  30
  31 static u32 gpiointmask = 0, gpiointval = 0;
  32
  33 static inline void ar5315_gpio_irq(void)
  34 {
  35         u32 pend;
  36         sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~AR5315_ISR_GPIO);
  37
  38         /* only do one gpio interrupt at a time */
  39         pend = (sysRegRead(AR5315_GPIO_DI) ^ gpiointval) & gpiointmask;
  40         if (!pend)
  41                 return;
  42
  43         do_IRQ(AR531X_GPIO_IRQ_BASE + fls(pend) - 1);
  44 }
  45
  46
  47 /*
  48  * Called when an interrupt is received, this function
  49  * determines exactly which interrupt it was, and it
  50  * invokes the appropriate handler.
  51  *
  52  * Implicitly, we also define interrupt priority by
  53  * choosing which to dispatch first.
  54  */
  55 asmlinkage void ar5315_irq_dispatch(void)
  56 {
  57         int pending = read_c0_status() & read_c0_cause();
  58
  59         if (pending & CAUSEF_IP3)
  60                 do_IRQ(AR5315_IRQ_WLAN0_INTRS);
  61         else if (pending & CAUSEF_IP4)
  62                 do_IRQ(AR5315_IRQ_ENET0_INTRS);
  63         else if (pending & CAUSEF_IP2) {
  64                 unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
  65
  66                 if (ar531x_misc_intrs & AR5315_ISR_SPI)
  67                         do_IRQ(AR531X_MISC_IRQ_SPI);
  68                 else if (ar531x_misc_intrs & AR5315_ISR_TIMER)
  69                         do_IRQ(AR531X_MISC_IRQ_TIMER);
  70                 else if (ar531x_misc_intrs & AR5315_ISR_AHB)
  71                         do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
  72                 else if (ar531x_misc_intrs & AR5315_ISR_GPIO)
  73                         ar5315_gpio_irq();
  74                 else if (ar531x_misc_intrs & AR5315_ISR_UART0)
  75                         do_IRQ(AR531X_MISC_IRQ_UART0);
  76                 else if (ar531x_misc_intrs & AR5315_ISR_WD)
  77                         do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
  78                 else
  79                         do_IRQ(AR531X_MISC_IRQ_NONE);
  80         } else if (pending & CAUSEF_IP7)
  81                 do_IRQ(AR531X_IRQ_CPU_CLOCK);
  82 }
  83
  84 static void ar5315_gpio_intr_enable(unsigned int irq)
  85 {
  86         u32 gpio, mask;
  87         gpio = irq - AR531X_GPIO_IRQ_BASE;
  88         mask = 1 << gpio;
  89         gpiointmask |= mask;
  90
  91         /* reconfigure GPIO line as input */
  92         sysRegMask(AR5315_GPIO_CR, AR5315_GPIO_CR_M(gpio), AR5315_GPIO_CR_I(gpio));
  93
  94         /* Enable interrupt with edge detection */
  95         sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(3));
  96 }
  97
  98 static void ar5315_gpio_intr_disable(unsigned int irq)
  99 {
 100         u32 gpio, mask;
 101         gpio = irq - AR531X_GPIO_IRQ_BASE;
 102         mask = 1 << gpio;
 103
 104         gpiointmask &= ~mask;
 105
 106         /* Disable interrupt with edge detection */
 107         sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(0));
 108 }
 109
 110 /* Turn on the specified AR531X_MISC_IRQ interrupt */
 111 static unsigned int ar5315_gpio_intr_startup(unsigned int irq)
 112 {
 113         ar5315_gpio_intr_enable(irq);
 114         return 0;
 115 }
 116
 117 /* Turn off the specified AR531X_MISC_IRQ interrupt */
 118 static void
 119 ar5315_gpio_intr_shutdown(unsigned int irq)
 120 {
 121         ar5315_gpio_intr_disable(irq);
 122 }
 123
 124 static void
 125 ar5315_gpio_intr_ack(unsigned int irq)
 126 {
 127         ar5315_gpio_intr_disable(irq);
 128 }
 129
 130 static void
 131 ar5315_gpio_intr_end(unsigned int irq)
 132 {
 133         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 134                 ar5315_gpio_intr_enable(irq);
 135 }
 136
 137 static struct irq_chip ar5315_gpio_intr_controller = {
 138         .typename       = "AR5315 GPIO",
 139         .startup        = ar5315_gpio_intr_startup,
 140         .shutdown       = ar5315_gpio_intr_shutdown,
 141         .enable         = ar5315_gpio_intr_enable,
 142         .disable        = ar5315_gpio_intr_disable,
 143         .ack            = ar5315_gpio_intr_ack,
 144         .end            = ar5315_gpio_intr_end,
 145 };
 146
 147
 148 /* Enable the specified AR531X_MISC_IRQ interrupt */
 149 static void
 150 ar5315_misc_intr_enable(unsigned int irq)
 151 {
 152         unsigned int imr;
 153
 154         imr = sysRegRead(AR5315_IMR);
 155         switch(irq)
 156         {
 157            case AR531X_MISC_IRQ_SPI:
 158                  imr |= AR5315_ISR_SPI;
 159                  break;
 160
 161            case AR531X_MISC_IRQ_TIMER:
 162              imr |= AR5315_ISR_TIMER;
 163              break;
 164
 165            case AR531X_MISC_IRQ_AHB_PROC:
 166              imr |= AR5315_ISR_AHB;
 167              break;
 168
 169            case AR531X_MISC_IRQ_AHB_DMA:
 170              imr |= 0/* ?? */;
 171              break;
 172
 173            case AR531X_MISC_IRQ_GPIO:
 174              imr |= AR5315_ISR_GPIO;
 175              break;
 176
 177            case AR531X_MISC_IRQ_UART0:
 178              imr |= AR5315_ISR_UART0;
 179              break;
 180
 181
 182            case AR531X_MISC_IRQ_WATCHDOG:
 183              imr |= AR5315_ISR_WD;
 184              break;
 185
 186            case AR531X_MISC_IRQ_LOCAL:
 187              imr |= 0/* ?? */;
 188              break;
 189
 190         }
 191         sysRegWrite(AR5315_IMR, imr);
 192         imr=sysRegRead(AR5315_IMR); /* flush write buffer */
 193 }
 194
 195 /* Disable the specified AR531X_MISC_IRQ interrupt */
 196 static void
 197 ar5315_misc_intr_disable(unsigned int irq)
 198 {
 199         unsigned int imr;
 200
 201         imr = sysRegRead(AR5315_IMR);
 202         switch(irq)
 203         {
 204            case AR531X_MISC_IRQ_SPI:
 205                  imr &= ~AR5315_ISR_SPI;
 206                  break;
 207
 208            case AR531X_MISC_IRQ_TIMER:
 209              imr &= (~AR5315_ISR_TIMER);
 210              break;
 211
 212            case AR531X_MISC_IRQ_AHB_PROC:
 213              imr &= (~AR5315_ISR_AHB);
 214              break;
 215
 216            case AR531X_MISC_IRQ_AHB_DMA:
 217              imr &= 0/* ?? */;
 218              break;
 219
 220            case AR531X_MISC_IRQ_GPIO:
 221              imr &= ~AR5315_ISR_GPIO;
 222              break;
 223
 224            case AR531X_MISC_IRQ_UART0:
 225              imr &= (~AR5315_ISR_UART0);
 226              break;
 227
 228            case AR531X_MISC_IRQ_WATCHDOG:
 229              imr &= (~AR5315_ISR_WD);
 230              break;
 231
 232            case AR531X_MISC_IRQ_LOCAL:
 233              imr &= ~0/* ?? */;
 234              break;
 235
 236         }
 237         sysRegWrite(AR5315_IMR, imr);
 238         sysRegRead(AR5315_IMR); /* flush write buffer */
 239 }
 240
 241 /* Turn on the specified AR531X_MISC_IRQ interrupt */
 242 static unsigned int
 243 ar5315_misc_intr_startup(unsigned int irq)
 244 {
 245         ar5315_misc_intr_enable(irq);
 246         return 0;
 247 }
 248
 249 /* Turn off the specified AR531X_MISC_IRQ interrupt */
 250 static void
 251 ar5315_misc_intr_shutdown(unsigned int irq)
 252 {
 253         ar5315_misc_intr_disable(irq);
 254 }
 255
 256 static void
 257 ar5315_misc_intr_ack(unsigned int irq)
 258 {
 259         ar5315_misc_intr_disable(irq);
 260 }
 261
 262 static void
 263 ar5315_misc_intr_end(unsigned int irq)
 264 {
 265         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 266                 ar5315_misc_intr_enable(irq);
 267 }
 268
 269 static struct irq_chip ar5315_misc_intr_controller = {
 270         .typename       = "AR5315 misc",
 271         .startup        = ar5315_misc_intr_startup,
 272         .shutdown       = ar5315_misc_intr_shutdown,
 273         .enable         = ar5315_misc_intr_enable,
 274         .disable        = ar5315_misc_intr_disable,
 275         .ack            = ar5315_misc_intr_ack,
 276         .end            = ar5315_misc_intr_end,
 277 };
 278
 279 static irqreturn_t ar5315_ahb_proc_handler(int cpl, void *dev_id)
 280 {
 281     sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
 282     sysRegRead(AR5315_AHB_ERR1);
 283
 284     printk("AHB fatal error\n");
 285     machine_restart("AHB error"); /* Catastrophic failure */
 286
 287     return IRQ_HANDLED;
 288 }
 289
 290 static struct irqaction ar5315_ahb_proc_interrupt  = {
 291         .handler        = ar5315_ahb_proc_handler,
 292         .flags          = IRQF_DISABLED,
 293         .name           = "ar5315_ahb_proc_interrupt",
 294 };
 295
 296
 297 static struct irqaction cascade  = {
 298         .handler        = no_action,
 299         .flags          = IRQF_DISABLED,
 300         .name           = "cascade",
 301 };
 302
 303 static void ar5315_gpio_intr_init(int irq_base)
 304 {
 305         int i;
 306
 307         for (i = irq_base; i < irq_base + AR531X_GPIO_IRQ_COUNT; i++) {
 308                 irq_desc[i].status = IRQ_DISABLED;
 309                 irq_desc[i].action = NULL;
 310                 irq_desc[i].depth = 1;
 311                 irq_desc[i].chip = &ar5315_gpio_intr_controller;
 312         }
 313         setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
 314         gpiointval = sysRegRead(AR5315_GPIO_DI);
 315 }
 316
 317 void ar5315_misc_intr_init(int irq_base)
 318 {
 319         int i;
 320
 321         for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
 322                 irq_desc[i].status = IRQ_DISABLED;
 323                 irq_desc[i].action = NULL;
 324                 irq_desc[i].depth = 1;
 325                 irq_desc[i].chip = &ar5315_misc_intr_controller;
 326         }
 327         setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt);
 328         setup_irq(AR5315_IRQ_MISC_INTRS, &cascade);
 329         ar5315_gpio_intr_init(AR531X_GPIO_IRQ_BASE);
 330 }
 331