1 --- a/drivers/mtd/devices/Kconfig
2 +++ b/drivers/mtd/devices/Kconfig
3 @@ -135,6 +135,10 @@ config MTD_BCM47XXSFLASH
4 registered by bcma as platform devices. This enables driver for
5 serial flash memories (only read-only mode is implemented).
8 + tristate "Atheros AR2315+ SPI Flash support"
9 + depends on ATHEROS_AR2315
12 tristate "Uncached system RAM"
14 --- a/drivers/mtd/devices/Makefile
15 +++ b/drivers/mtd/devices/Makefile
16 @@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_M25P80) += m25p80.o
17 obj-$(CONFIG_MTD_NAND_OMAP_BCH) += elm.o
18 obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
19 obj-$(CONFIG_MTD_SST25L) += sst25l.o
20 +obj-$(CONFIG_MTD_AR2315) += ar2315.o
21 obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
25 +++ b/drivers/mtd/devices/ar2315.c
29 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
31 + * Copyright (c) 2005-2006 Atheros Communications Inc.
32 + * Copyright (C) 2006-2007 FON Technology, SL.
33 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
37 + * This code is free software; you can redistribute it and/or modify
38 + * it under the terms of the GNU General Public License version 2 as
39 + * published by the Free Software Foundation.
43 +#include <linux/kernel.h>
44 +#include <linux/module.h>
45 +#include <linux/types.h>
46 +#include <linux/version.h>
47 +#include <linux/errno.h>
48 +#include <linux/slab.h>
49 +#include <linux/mtd/mtd.h>
50 +#include <linux/mtd/partitions.h>
51 +#include <linux/platform_device.h>
52 +#include <linux/sched.h>
53 +#include <linux/root_dev.h>
54 +#include <linux/delay.h>
55 +#include <linux/io.h>
57 +#include "ar2315_spiflash.h"
60 +#define SPIFLASH "spiflash: "
61 +#define busy_wait(_priv, _condition, _wait) do { \
62 + while (_condition) { \
63 + spin_unlock_bh(&_priv->lock); \
66 + else if ((_wait == 1) && need_resched()) \
70 + spin_lock_bh(&_priv->lock); \
83 +/* Flash configuration table */
90 +static const struct flashconfig flashconfig_tbl[] = {
91 + [FLASH_NONE] = { 0, 0, 0},
92 + [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
93 + STM_1MB_SECTOR_SIZE},
94 + [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
95 + STM_2MB_SECTOR_SIZE},
96 + [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
97 + STM_4MB_SECTOR_SIZE},
98 + [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
99 + STM_8MB_SECTOR_SIZE},
100 + [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
101 + STM_16MB_SECTOR_SIZE}
104 +/* Mapping of generic opcodes to STM serial flash opcodes */
125 +static const struct opcodes stm_opcodes[] = {
126 + [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
127 + [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
128 + [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
129 + [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
130 + [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
131 + [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
132 + [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
133 + [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
134 + [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
135 + [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
136 + [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
139 +/* Driver private data structure */
140 +struct spiflash_priv {
141 + struct mtd_info mtd;
142 + void __iomem *readaddr; /* memory mapped data for read */
143 + void __iomem *mmraddr; /* memory mapped register space */
144 + wait_queue_head_t wq;
149 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
158 +/*****************************************************************************/
161 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
163 + return ioread32(priv->mmraddr + reg);
167 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
169 + iowrite32(data, priv->mmraddr + reg);
173 +spiflash_wait_busy(struct spiflash_priv *priv)
177 + busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
183 +spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
185 + const struct opcodes *op;
188 + op = &stm_opcodes[opcode];
189 + reg = spiflash_wait_busy(priv);
190 + spiflash_write_reg(priv, SPI_FLASH_OPCODE,
191 + ((u32) op->code) | (addr << 8));
193 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
194 + reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
196 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
197 + spiflash_wait_busy(priv);
202 + reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
204 + switch (op->rx_cnt) {
225 + * Probe SPI flash device
226 + * Function returns 0 for failure.
227 + * and flashconfig_tbl array index for success.
230 +spiflash_probe_chip(struct spiflash_priv *priv)
235 + /* Read the signature on the flash device */
236 + spin_lock_bh(&priv->lock);
237 + sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
238 + spin_unlock_bh(&priv->lock);
241 + case STM_8MBIT_SIGNATURE:
242 + flash_size = FLASH_1MB;
244 + case STM_16MBIT_SIGNATURE:
245 + flash_size = FLASH_2MB;
247 + case STM_32MBIT_SIGNATURE:
248 + flash_size = FLASH_4MB;
250 + case STM_64MBIT_SIGNATURE:
251 + flash_size = FLASH_8MB;
253 + case STM_128MBIT_SIGNATURE:
254 + flash_size = FLASH_16MB;
257 + pr_warn(SPIFLASH "Read of flash device signature failed!\n");
265 +/* wait until the flash chip is ready and grab a lock */
266 +static int spiflash_wait_ready(struct spiflash_priv *priv, int state)
268 + DECLARE_WAITQUEUE(wait, current);
271 + spin_lock_bh(&priv->lock);
272 + if (priv->state != FL_READY) {
273 + set_current_state(TASK_UNINTERRUPTIBLE);
274 + add_wait_queue(&priv->wq, &wait);
275 + spin_unlock_bh(&priv->lock);
277 + remove_wait_queue(&priv->wq, &wait);
279 + if (signal_pending(current))
284 + priv->state = state;
289 +static inline void spiflash_done(struct spiflash_priv *priv)
291 + priv->state = FL_READY;
292 + spin_unlock_bh(&priv->lock);
293 + wake_up(&priv->wq);
297 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
299 + busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
300 + SPI_STATUS_WIP, timeout);
301 + spiflash_done(priv);
307 +spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
309 + struct spiflash_priv *priv = to_spiflash(mtd);
310 + const struct opcodes *op;
313 + if (instr->addr + instr->len > mtd->size)
316 + if (!spiflash_wait_ready(priv, FL_ERASING))
319 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
320 + reg = spiflash_wait_busy(priv);
322 + op = &stm_opcodes[SPI_SECTOR_ERASE];
323 + temp = ((u32)instr->addr << 8) | (u32)(op->code);
324 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
326 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
327 + reg |= op->tx_cnt | SPI_CTL_START;
328 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
330 + spiflash_wait_complete(priv, 20);
332 + instr->state = MTD_ERASE_DONE;
333 + mtd_erase_callback(instr);
339 +spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
342 + struct spiflash_priv *priv = to_spiflash(mtd);
347 + if (from + len > mtd->size)
352 + if (!spiflash_wait_ready(priv, FL_READING))
355 + memcpy_fromio(buf, priv->readaddr + from, len);
356 + spiflash_done(priv);
362 +spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
365 + struct spiflash_priv *priv = to_spiflash(mtd);
366 + u32 opcode, bytes_left;
373 + if (to + len > mtd->size)
379 + u32 read_len, reg, page_offset, spi_data = 0;
381 + read_len = min(bytes_left, sizeof(u32));
383 + /* 32-bit writes cannot span across a page boundary
384 + * (256 bytes). This types of writes require two page
385 + * program operations to handle it correctly. The STM part
386 + * will write the overflow data to the beginning of the
387 + * current page as opposed to the subsequent page.
389 + page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
391 + if (page_offset > STM_PAGE_SIZE)
392 + read_len -= (page_offset - STM_PAGE_SIZE);
394 + if (!spiflash_wait_ready(priv, FL_WRITING))
397 + spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
399 + switch (read_len) {
401 + spi_data |= buf[3] << 24;
404 + spi_data |= buf[2] << 16;
407 + spi_data |= buf[1] << 8;
410 + spi_data |= buf[0] & 0xff;
416 + spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
417 + opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
418 + (to & 0x00ffffff) << 8;
419 + spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
421 + reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
422 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
423 + reg |= (read_len + 4) | SPI_CTL_START;
424 + spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
426 + spiflash_wait_complete(priv, 1);
428 + bytes_left -= read_len;
432 + *retlen += read_len;
433 + } while (bytes_left != 0);
439 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
440 +static const char * const part_probe_types[] = {
441 + "cmdlinepart", "RedBoot", "MyLoader", NULL
447 +spiflash_probe(struct platform_device *pdev)
449 + struct spiflash_priv *priv;
450 + struct mtd_info *mtd;
451 + struct resource *res;
455 + priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL);
456 + spin_lock_init(&priv->lock);
457 + init_waitqueue_head(&priv->wq);
458 + priv->state = FL_READY;
461 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
463 + dev_err(&pdev->dev, "No MMR resource found\n");
467 + priv->mmraddr = ioremap_nocache(res->start, resource_size(res));
468 + if (!priv->mmraddr) {
469 + dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
473 + index = spiflash_probe_chip(priv);
475 + dev_warn(&pdev->dev, SPIFLASH "Found no flash device\n");
479 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
481 + dev_err(&pdev->dev, "No flash readmem resource found\n");
485 + priv->readaddr = ioremap_nocache(res->start,
486 + flashconfig_tbl[index].byte_cnt);
487 + if (!priv->readaddr) {
488 + dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n");
492 + platform_set_drvdata(pdev, priv);
493 + mtd->name = "spiflash";
494 + mtd->type = MTD_NORFLASH;
495 + mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
496 + mtd->size = flashconfig_tbl[index].byte_cnt;
497 + mtd->erasesize = flashconfig_tbl[index].sector_size;
498 + mtd->writesize = 1;
499 + mtd->numeraseregions = 0;
500 + mtd->eraseregions = NULL;
501 + mtd->_erase = spiflash_erase;
502 + mtd->_read = spiflash_read;
503 + mtd->_write = spiflash_write;
504 + mtd->owner = THIS_MODULE;
506 + dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
508 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
509 + /* parse redboot partitions */
511 + result = mtd_device_parse_register(mtd, part_probe_types,
519 + iounmap(priv->mmraddr);
525 +spiflash_remove(struct platform_device *pdev)
527 + struct spiflash_priv *priv = platform_get_drvdata(pdev);
528 + struct mtd_info *mtd = &priv->mtd;
530 + mtd_device_unregister(mtd);
531 + iounmap(priv->mmraddr);
532 + iounmap(priv->readaddr);
538 +static struct platform_driver spiflash_driver = {
539 + .driver.name = "ar2315-spiflash",
540 + .probe = spiflash_probe,
541 + .remove = spiflash_remove,
547 + return platform_driver_register(&spiflash_driver);
553 + return platform_driver_unregister(&spiflash_driver);
556 +module_init(spiflash_init);
557 +module_exit(spiflash_exit);
559 +MODULE_LICENSE("GPL");
560 +MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
561 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
564 +++ b/drivers/mtd/devices/ar2315_spiflash.h
567 + * Atheros AR2315 SPI Flash Memory support header file.
569 + * Copyright (c) 2005, Atheros Communications Inc.
570 + * Copyright (C) 2006 FON Technology, SL.
571 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
572 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
574 + * This code is free software; you can redistribute it and/or modify
575 + * it under the terms of the GNU General Public License version 2 as
576 + * published by the Free Software Foundation.
579 +#ifndef __AR2315_SPIFLASH_H
580 +#define __AR2315_SPIFLASH_H
582 +#define STM_PAGE_SIZE 256
584 +#define SFI_WRITE_BUFFER_SIZE 4
585 +#define SFI_FLASH_ADDR_MASK 0x00ffffff
587 +#define STM_8MBIT_SIGNATURE 0x13
588 +#define STM_M25P80_BYTE_COUNT 1048576
589 +#define STM_M25P80_SECTOR_COUNT 16
590 +#define STM_M25P80_SECTOR_SIZE 0x10000
592 +#define STM_16MBIT_SIGNATURE 0x14
593 +#define STM_M25P16_BYTE_COUNT 2097152
594 +#define STM_M25P16_SECTOR_COUNT 32
595 +#define STM_M25P16_SECTOR_SIZE 0x10000
597 +#define STM_32MBIT_SIGNATURE 0x15
598 +#define STM_M25P32_BYTE_COUNT 4194304
599 +#define STM_M25P32_SECTOR_COUNT 64
600 +#define STM_M25P32_SECTOR_SIZE 0x10000
602 +#define STM_64MBIT_SIGNATURE 0x16
603 +#define STM_M25P64_BYTE_COUNT 8388608
604 +#define STM_M25P64_SECTOR_COUNT 128
605 +#define STM_M25P64_SECTOR_SIZE 0x10000
607 +#define STM_128MBIT_SIGNATURE 0x17
608 +#define STM_M25P128_BYTE_COUNT 16777216
609 +#define STM_M25P128_SECTOR_COUNT 256
610 +#define STM_M25P128_SECTOR_SIZE 0x10000
612 +#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
613 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
614 +#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
615 +#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
616 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
617 +#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
618 +#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
619 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
620 +#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
621 +#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
622 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
623 +#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
624 +#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
625 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
626 +#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
629 + * ST Microelectronics Opcodes for Serial Flash
632 +#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
633 +#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
634 +#define STM_OP_RD_STATUS 0x05 /* Read Status */
635 +#define STM_OP_WR_STATUS 0x01 /* Write Status */
636 +#define STM_OP_RD_DATA 0x03 /* Read Data */
637 +#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
638 +#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
639 +#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
640 +#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
641 +#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
642 +#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
644 +#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
645 +#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
646 +#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
647 +#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
648 +#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
649 +#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
652 + * SPI Flash Interface Registers
655 +#define SPI_FLASH_CTL 0x00
656 +#define SPI_FLASH_OPCODE 0x04
657 +#define SPI_FLASH_DATA 0x08
659 +#define SPI_CTL_START 0x00000100
660 +#define SPI_CTL_BUSY 0x00010000
661 +#define SPI_CTL_TXCNT_MASK 0x0000000f
662 +#define SPI_CTL_RXCNT_MASK 0x000000f0
663 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
664 +#define SPI_CTL_SIZE_MASK 0x00060000
666 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
667 +#define SPI_OPCODE_MASK 0x000000ff
669 +#define SPI_STATUS_WIP STM_STATUS_WIP