target/linux/atheros/patches-3.14/120-spiflash.patch

   1 --- a/drivers/mtd/devices/Kconfig
   2 +++ b/drivers/mtd/devices/Kconfig
   3 @@ -128,6 +128,10 @@ config MTD_BCM47XXSFLASH
   4           registered by bcma as platform devices. This enables driver for
   5           serial flash memories (only read-only mode is implemented).
   6
   7 +config MTD_AR2315
   8 +       tristate "Atheros AR2315+ SPI Flash support"
   9 +       depends on ATHEROS_AR2315
  10 +
  11  config MTD_SLRAM
  12         tristate "Uncached system RAM"
  13         help
  14 --- a/drivers/mtd/devices/Makefile
  15 +++ b/drivers/mtd/devices/Makefile
  16 @@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_M25P80)      += m25p80.o
  17  obj-$(CONFIG_MTD_NAND_OMAP_BCH)        += elm.o
  18  obj-$(CONFIG_MTD_SPEAR_SMI)    += spear_smi.o
  19  obj-$(CONFIG_MTD_SST25L)       += sst25l.o
  20 +obj-$(CONFIG_MTD_AR2315)       += ar2315.o
  21  obj-$(CONFIG_MTD_BCM47XXSFLASH)        += bcm47xxsflash.o
  22
  23
  24 --- /dev/null
  25 +++ b/drivers/mtd/devices/ar2315.c
  26 @@ -0,0 +1,461 @@
  27 +
  28 +/*
  29 + * MTD driver for the SPI Flash Memory support on Atheros AR2315
  30 + *
  31 + * Copyright (c) 2005-2006 Atheros Communications Inc.
  32 + * Copyright (C) 2006-2007 FON Technology, SL.
  33 + * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
  34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
  35 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
  36 + *
  37 + * This code is free software; you can redistribute it and/or modify
  38 + * it under the terms of the GNU General Public License version 2 as
  39 + * published by the Free Software Foundation.
  40 + *
  41 + */
  42 +
  43 +#include <linux/kernel.h>
  44 +#include <linux/module.h>
  45 +#include <linux/types.h>
  46 +#include <linux/version.h>
  47 +#include <linux/errno.h>
  48 +#include <linux/slab.h>
  49 +#include <linux/mtd/mtd.h>
  50 +#include <linux/mtd/partitions.h>
  51 +#include <linux/platform_device.h>
  52 +#include <linux/sched.h>
  53 +#include <linux/root_dev.h>
  54 +#include <linux/delay.h>
  55 +#include <linux/io.h>
  56 +#include <linux/mutex.h>
  57 +
  58 +#include "ar2315_spiflash.h"
  59 +
  60 +#define DRIVER_NAME "ar2315-spiflash"
  61 +
  62 +#define busy_wait(_priv, _condition, _wait) do { \
  63 +       while (_condition) { \
  64 +               if (_wait > 1) \
  65 +                       msleep(_wait); \
  66 +               else if ((_wait == 1) && need_resched()) \
  67 +                       schedule(); \
  68 +               else \
  69 +                       udelay(1); \
  70 +       } \
  71 +} while (0)
  72 +
  73 +enum {
  74 +       FLASH_NONE,
  75 +       FLASH_1MB,
  76 +       FLASH_2MB,
  77 +       FLASH_4MB,
  78 +       FLASH_8MB,
  79 +       FLASH_16MB,
  80 +};
  81 +
  82 +/* Flash configuration table */
  83 +struct flashconfig {
  84 +       u32 byte_cnt;
  85 +       u32 sector_cnt;
  86 +       u32 sector_size;
  87 +};
  88 +
  89 +static const struct flashconfig flashconfig_tbl[] = {
  90 +       [FLASH_NONE] = { 0, 0, 0},
  91 +       [FLASH_1MB]  = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
  92 +                        STM_1MB_SECTOR_SIZE},
  93 +       [FLASH_2MB]  = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
  94 +                        STM_2MB_SECTOR_SIZE},
  95 +       [FLASH_4MB]  = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
  96 +                        STM_4MB_SECTOR_SIZE},
  97 +       [FLASH_8MB]  = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
  98 +                        STM_8MB_SECTOR_SIZE},
  99 +       [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
 100 +                        STM_16MB_SECTOR_SIZE}
 101 +};
 102 +
 103 +/* Mapping of generic opcodes to STM serial flash opcodes */
 104 +enum {
 105 +       SPI_WRITE_ENABLE,
 106 +       SPI_WRITE_DISABLE,
 107 +       SPI_RD_STATUS,
 108 +       SPI_WR_STATUS,
 109 +       SPI_RD_DATA,
 110 +       SPI_FAST_RD_DATA,
 111 +       SPI_PAGE_PROGRAM,
 112 +       SPI_SECTOR_ERASE,
 113 +       SPI_BULK_ERASE,
 114 +       SPI_DEEP_PWRDOWN,
 115 +       SPI_RD_SIG,
 116 +};
 117 +
 118 +struct opcodes {
 119 +       __u16 code;
 120 +       __s8 tx_cnt;
 121 +       __s8 rx_cnt;
 122 +};
 123 +
 124 +static const struct opcodes stm_opcodes[] = {
 125 +       [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
 126 +       [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
 127 +       [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
 128 +       [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
 129 +       [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
 130 +       [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
 131 +       [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
 132 +       [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
 133 +       [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
 134 +       [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
 135 +       [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
 136 +};
 137 +
 138 +/* Driver private data structure */
 139 +struct spiflash_priv {
 140 +       struct mtd_info mtd;
 141 +       void __iomem *readaddr; /* memory mapped data for read  */
 142 +       void __iomem *mmraddr;  /* memory mapped register space */
 143 +       struct mutex lock;      /* serialize registers access */
 144 +};
 145 +
 146 +#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
 147 +
 148 +enum {
 149 +       FL_READY,
 150 +       FL_READING,
 151 +       FL_ERASING,
 152 +       FL_WRITING
 153 +};
 154 +
 155 +/*****************************************************************************/
 156 +
 157 +static u32
 158 +spiflash_read_reg(struct spiflash_priv *priv, int reg)
 159 +{
 160 +       return ioread32(priv->mmraddr + reg);
 161 +}
 162 +
 163 +static void
 164 +spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
 165 +{
 166 +       iowrite32(data, priv->mmraddr + reg);
 167 +}
 168 +
 169 +static u32
 170 +spiflash_wait_busy(struct spiflash_priv *priv)
 171 +{
 172 +       u32 reg;
 173 +
 174 +       busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
 175 +               SPI_CTL_BUSY, 0);
 176 +       return reg;
 177 +}
 178 +
 179 +static u32
 180 +spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
 181 +{
 182 +       const struct opcodes *op;
 183 +       u32 reg, mask;
 184 +
 185 +       op = &stm_opcodes[opcode];
 186 +       reg = spiflash_wait_busy(priv);
 187 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE,
 188 +               ((u32) op->code) | (addr << 8));
 189 +
 190 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 191 +       reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
 192 +
 193 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 194 +       spiflash_wait_busy(priv);
 195 +
 196 +       if (!op->rx_cnt)
 197 +               return 0;
 198 +
 199 +       reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
 200 +
 201 +       switch (op->rx_cnt) {
 202 +       case 1:
 203 +               mask = 0x000000ff;
 204 +               break;
 205 +       case 2:
 206 +               mask = 0x0000ffff;
 207 +               break;
 208 +       case 3:
 209 +               mask = 0x00ffffff;
 210 +               break;
 211 +       default:
 212 +               mask = 0xffffffff;
 213 +               break;
 214 +       }
 215 +       reg &= mask;
 216 +
 217 +       return reg;
 218 +}
 219 +
 220 +/*
 221 + * Probe SPI flash device
 222 + * Function returns 0 for failure.
 223 + * and flashconfig_tbl array index for success.
 224 + */
 225 +static int
 226 +spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)
 227 +{
 228 +       u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
 229 +       int flash_size;
 230 +
 231 +       switch (sig) {
 232 +       case STM_8MBIT_SIGNATURE:
 233 +               flash_size = FLASH_1MB;
 234 +               break;
 235 +       case STM_16MBIT_SIGNATURE:
 236 +               flash_size = FLASH_2MB;
 237 +               break;
 238 +       case STM_32MBIT_SIGNATURE:
 239 +               flash_size = FLASH_4MB;
 240 +               break;
 241 +       case STM_64MBIT_SIGNATURE:
 242 +               flash_size = FLASH_8MB;
 243 +               break;
 244 +       case STM_128MBIT_SIGNATURE:
 245 +               flash_size = FLASH_16MB;
 246 +               break;
 247 +       default:
 248 +               dev_warn(&pdev->dev, "read of flash device signature failed!\n");
 249 +               return 0;
 250 +       }
 251 +
 252 +       return flash_size;
 253 +}
 254 +
 255 +static void
 256 +spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
 257 +{
 258 +       busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
 259 +               SPI_STATUS_WIP, timeout);
 260 +}
 261 +
 262 +static int
 263 +spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
 264 +{
 265 +       struct spiflash_priv *priv = to_spiflash(mtd);
 266 +       const struct opcodes *op;
 267 +       u32 temp, reg;
 268 +
 269 +       if (instr->addr + instr->len > mtd->size)
 270 +               return -EINVAL;
 271 +
 272 +       mutex_lock(&priv->lock);
 273 +
 274 +       spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 275 +       reg = spiflash_wait_busy(priv);
 276 +
 277 +       op = &stm_opcodes[SPI_SECTOR_ERASE];
 278 +       temp = ((u32)instr->addr << 8) | (u32)(op->code);
 279 +       spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
 280 +
 281 +       reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 282 +       reg |= op->tx_cnt | SPI_CTL_START;
 283 +       spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 284 +
 285 +       spiflash_wait_complete(priv, 20);
 286 +
 287 +       mutex_unlock(&priv->lock);
 288 +
 289 +       instr->state = MTD_ERASE_DONE;
 290 +       mtd_erase_callback(instr);
 291 +
 292 +       return 0;
 293 +}
 294 +
 295 +static int
 296 +spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
 297 +             u_char *buf)
 298 +{
 299 +       struct spiflash_priv *priv = to_spiflash(mtd);
 300 +
 301 +       if (!len)
 302 +               return 0;
 303 +
 304 +       if (from + len > mtd->size)
 305 +               return -EINVAL;
 306 +
 307 +       *retlen = len;
 308 +
 309 +       mutex_lock(&priv->lock);
 310 +
 311 +       memcpy_fromio(buf, priv->readaddr + from, len);
 312 +
 313 +       mutex_unlock(&priv->lock);
 314 +
 315 +       return 0;
 316 +}
 317 +
 318 +static int
 319 +spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
 320 +              const u8 *buf)
 321 +{
 322 +       struct spiflash_priv *priv = to_spiflash(mtd);
 323 +       u32 opcode, bytes_left;
 324 +
 325 +       *retlen = 0;
 326 +
 327 +       if (!len)
 328 +               return 0;
 329 +
 330 +       if (to + len > mtd->size)
 331 +               return -EINVAL;
 332 +
 333 +       bytes_left = len;
 334 +
 335 +       do {
 336 +               u32 read_len, reg, page_offset, spi_data = 0;
 337 +
 338 +               read_len = min(bytes_left, sizeof(u32));
 339 +
 340 +               /* 32-bit writes cannot span across a page boundary
 341 +                * (256 bytes). This types of writes require two page
 342 +                * program operations to handle it correctly. The STM part
 343 +                * will write the overflow data to the beginning of the
 344 +                * current page as opposed to the subsequent page.
 345 +                */
 346 +               page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
 347 +
 348 +               if (page_offset > STM_PAGE_SIZE)
 349 +                       read_len -= (page_offset - STM_PAGE_SIZE);
 350 +
 351 +               mutex_lock(&priv->lock);
 352 +
 353 +               spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
 354 +               spi_data = 0;
 355 +               switch (read_len) {
 356 +               case 4:
 357 +                       spi_data |= buf[3] << 24;
 358 +                       /* fall through */
 359 +               case 3:
 360 +                       spi_data |= buf[2] << 16;
 361 +                       /* fall through */
 362 +               case 2:
 363 +                       spi_data |= buf[1] << 8;
 364 +                       /* fall through */
 365 +               case 1:
 366 +                       spi_data |= buf[0] & 0xff;
 367 +                       break;
 368 +               default:
 369 +                       break;
 370 +               }
 371 +
 372 +               spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
 373 +               opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
 374 +                       (to & 0x00ffffff) << 8;
 375 +               spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
 376 +
 377 +               reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
 378 +               reg &= ~SPI_CTL_TX_RX_CNT_MASK;
 379 +               reg |= (read_len + 4) | SPI_CTL_START;
 380 +               spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
 381 +
 382 +               spiflash_wait_complete(priv, 1);
 383 +
 384 +               mutex_unlock(&priv->lock);
 385 +
 386 +               bytes_left -= read_len;
 387 +               to += read_len;
 388 +               buf += read_len;
 389 +
 390 +               *retlen += read_len;
 391 +       } while (bytes_left != 0);
 392 +
 393 +       return 0;
 394 +}
 395 +
 396 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
 397 +static const char * const part_probe_types[] = {
 398 +       "cmdlinepart", "RedBoot", "MyLoader", NULL
 399 +};
 400 +#endif
 401 +
 402 +static int
 403 +spiflash_probe(struct platform_device *pdev)
 404 +{
 405 +       struct spiflash_priv *priv;
 406 +       struct mtd_info *mtd;
 407 +       struct resource *res;
 408 +       int index;
 409 +       int result = 0;
 410 +
 411 +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 412 +       if (!priv)
 413 +               return -ENOMEM;
 414 +
 415 +       mutex_init(&priv->lock);
 416 +       mtd = &priv->mtd;
 417 +
 418 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 419 +       priv->mmraddr = devm_ioremap_resource(&pdev->dev, res);
 420 +       if (IS_ERR(priv->mmraddr)) {
 421 +               dev_warn(&pdev->dev, "failed to map flash MMR\n");
 422 +               return PTR_ERR(priv->mmraddr);
 423 +       }
 424 +
 425 +       index = spiflash_probe_chip(pdev, priv);
 426 +       if (!index) {
 427 +               dev_warn(&pdev->dev, "found no flash device\n");
 428 +               return -ENODEV;
 429 +       }
 430 +
 431 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 432 +       priv->readaddr = devm_ioremap_resource(&pdev->dev, res);
 433 +       if (IS_ERR(priv->readaddr)) {
 434 +               dev_warn(&pdev->dev, "failed to map flash read mem\n");
 435 +               return PTR_ERR(priv->readaddr);
 436 +       }
 437 +
 438 +       platform_set_drvdata(pdev, priv);
 439 +       mtd->name = "spiflash";
 440 +       mtd->type = MTD_NORFLASH;
 441 +       mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
 442 +       mtd->size = flashconfig_tbl[index].byte_cnt;
 443 +       mtd->erasesize = flashconfig_tbl[index].sector_size;
 444 +       mtd->writesize = 1;
 445 +       mtd->numeraseregions = 0;
 446 +       mtd->eraseregions = NULL;
 447 +       mtd->_erase = spiflash_erase;
 448 +       mtd->_read = spiflash_read;
 449 +       mtd->_write = spiflash_write;
 450 +       mtd->owner = THIS_MODULE;
 451 +
 452 +       dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
 453 +
 454 +#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
 455 +       /* parse redboot partitions */
 456 +
 457 +       result = mtd_device_parse_register(mtd, part_probe_types,
 458 +                       NULL, NULL, 0);
 459 +#endif
 460 +
 461 +       return result;
 462 +}
 463 +
 464 +static int
 465 +spiflash_remove(struct platform_device *pdev)
 466 +{
 467 +       struct spiflash_priv *priv = platform_get_drvdata(pdev);
 468 +
 469 +       mtd_device_unregister(&priv->mtd);
 470 +
 471 +       return 0;
 472 +}
 473 +
 474 +static struct platform_driver spiflash_driver = {
 475 +       .driver.name = DRIVER_NAME,
 476 +       .probe = spiflash_probe,
 477 +       .remove = spiflash_remove,
 478 +};
 479 +
 480 +module_platform_driver(spiflash_driver);
 481 +
 482 +MODULE_LICENSE("GPL");
 483 +MODULE_AUTHOR("OpenWrt.org");
 484 +MODULE_AUTHOR("Atheros Communications Inc");
 485 +MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC");
 486 +MODULE_ALIAS("platform:" DRIVER_NAME);
 487 +
 488 --- /dev/null
 489 +++ b/drivers/mtd/devices/ar2315_spiflash.h
 490 @@ -0,0 +1,106 @@
 491 +/*
 492 + * Atheros AR2315 SPI Flash Memory support header file.
 493 + *
 494 + * Copyright (c) 2005, Atheros Communications Inc.
 495 + * Copyright (C) 2006 FON Technology, SL.
 496 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 497 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
 498 + *
 499 + * This code is free software; you can redistribute it and/or modify
 500 + * it under the terms of the GNU General Public License version 2 as
 501 + * published by the Free Software Foundation.
 502 + *
 503 + */
 504 +#ifndef __AR2315_SPIFLASH_H
 505 +#define __AR2315_SPIFLASH_H
 506 +
 507 +#define STM_PAGE_SIZE           256
 508 +
 509 +#define SFI_WRITE_BUFFER_SIZE   4
 510 +#define SFI_FLASH_ADDR_MASK     0x00ffffff
 511 +
 512 +#define STM_8MBIT_SIGNATURE     0x13
 513 +#define STM_M25P80_BYTE_COUNT   1048576
 514 +#define STM_M25P80_SECTOR_COUNT 16
 515 +#define STM_M25P80_SECTOR_SIZE  0x10000
 516 +
 517 +#define STM_16MBIT_SIGNATURE    0x14
 518 +#define STM_M25P16_BYTE_COUNT   2097152
 519 +#define STM_M25P16_SECTOR_COUNT 32
 520 +#define STM_M25P16_SECTOR_SIZE  0x10000
 521 +
 522 +#define STM_32MBIT_SIGNATURE    0x15
 523 +#define STM_M25P32_BYTE_COUNT   4194304
 524 +#define STM_M25P32_SECTOR_COUNT 64
 525 +#define STM_M25P32_SECTOR_SIZE  0x10000
 526 +
 527 +#define STM_64MBIT_SIGNATURE    0x16
 528 +#define STM_M25P64_BYTE_COUNT   8388608
 529 +#define STM_M25P64_SECTOR_COUNT 128
 530 +#define STM_M25P64_SECTOR_SIZE  0x10000
 531 +
 532 +#define STM_128MBIT_SIGNATURE   0x17
 533 +#define STM_M25P128_BYTE_COUNT   16777216
 534 +#define STM_M25P128_SECTOR_COUNT 256
 535 +#define STM_M25P128_SECTOR_SIZE  0x10000
 536 +
 537 +#define STM_1MB_BYTE_COUNT   STM_M25P80_BYTE_COUNT
 538 +#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
 539 +#define STM_1MB_SECTOR_SIZE  STM_M25P80_SECTOR_SIZE
 540 +#define STM_2MB_BYTE_COUNT   STM_M25P16_BYTE_COUNT
 541 +#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
 542 +#define STM_2MB_SECTOR_SIZE  STM_M25P16_SECTOR_SIZE
 543 +#define STM_4MB_BYTE_COUNT   STM_M25P32_BYTE_COUNT
 544 +#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
 545 +#define STM_4MB_SECTOR_SIZE  STM_M25P32_SECTOR_SIZE
 546 +#define STM_8MB_BYTE_COUNT   STM_M25P64_BYTE_COUNT
 547 +#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
 548 +#define STM_8MB_SECTOR_SIZE  STM_M25P64_SECTOR_SIZE
 549 +#define STM_16MB_BYTE_COUNT   STM_M25P128_BYTE_COUNT
 550 +#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
 551 +#define STM_16MB_SECTOR_SIZE  STM_M25P128_SECTOR_SIZE
 552 +
 553 +/*
 554 + * ST Microelectronics Opcodes for Serial Flash
 555 + */
 556 +
 557 +#define STM_OP_WR_ENABLE       0x06     /* Write Enable */
 558 +#define STM_OP_WR_DISABLE      0x04     /* Write Disable */
 559 +#define STM_OP_RD_STATUS       0x05     /* Read Status */
 560 +#define STM_OP_WR_STATUS       0x01     /* Write Status */
 561 +#define STM_OP_RD_DATA         0x03     /* Read Data */
 562 +#define STM_OP_FAST_RD_DATA    0x0b     /* Fast Read Data */
 563 +#define STM_OP_PAGE_PGRM       0x02     /* Page Program */
 564 +#define STM_OP_SECTOR_ERASE    0xd8     /* Sector Erase */
 565 +#define STM_OP_BULK_ERASE      0xc7     /* Bulk Erase */
 566 +#define STM_OP_DEEP_PWRDOWN    0xb9     /* Deep Power-Down Mode */
 567 +#define STM_OP_RD_SIG          0xab     /* Read Electronic Signature */
 568 +
 569 +#define STM_STATUS_WIP       0x01       /* Write-In-Progress */
 570 +#define STM_STATUS_WEL       0x02       /* Write Enable Latch */
 571 +#define STM_STATUS_BP0       0x04       /* Block Protect 0 */
 572 +#define STM_STATUS_BP1       0x08       /* Block Protect 1 */
 573 +#define STM_STATUS_BP2       0x10       /* Block Protect 2 */
 574 +#define STM_STATUS_SRWD      0x80       /* Status Register Write Disable */
 575 +
 576 +/*
 577 + * SPI Flash Interface Registers
 578 + */
 579 +
 580 +#define SPI_FLASH_CTL           0x00
 581 +#define SPI_FLASH_OPCODE        0x04
 582 +#define SPI_FLASH_DATA          0x08
 583 +
 584 +#define SPI_CTL_START           0x00000100
 585 +#define SPI_CTL_BUSY            0x00010000
 586 +#define SPI_CTL_TXCNT_MASK      0x0000000f
 587 +#define SPI_CTL_RXCNT_MASK      0x000000f0
 588 +#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff
 589 +#define SPI_CTL_SIZE_MASK       0x00060000
 590 +
 591 +#define SPI_CTL_CLK_SEL_MASK    0x03000000
 592 +#define SPI_OPCODE_MASK         0x000000ff
 593 +
 594 +#define SPI_STATUS_WIP         STM_STATUS_WIP
 595 +
 596 +#endif