1 From ff78cbcd8d7d656a5f43abd2c744e610b8c6c740 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.org>
3 Date: Wed, 29 May 2019 13:54:21 +0100
4 Subject: [PATCH] ARM: dts: Add bcm2711-rpi-4-b.dts and components
6 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
8 arch/arm/boot/dts/Makefile | 1 +
9 arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 320 ++++++++++++
10 arch/arm/boot/dts/bcm2711.dtsi | 50 ++
11 arch/arm/boot/dts/bcm2838.dtsi | 724 ++++++++++++++++++++++++++
12 4 files changed, 1095 insertions(+)
13 create mode 100644 arch/arm/boot/dts/bcm2711-rpi-4-b.dts
14 create mode 100644 arch/arm/boot/dts/bcm2711.dtsi
15 create mode 100644 arch/arm/boot/dts/bcm2838.dtsi
17 --- a/arch/arm/boot/dts/Makefile
18 +++ b/arch/arm/boot/dts/Makefile
19 @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
20 bcm2708-rpi-zero-w.dtb \
23 + bcm2711-rpi-4-b.dtb \
24 bcm2710-rpi-3-b-plus.dtb \
28 +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
32 +#include "bcm2711.dtsi"
35 + compatible = "raspberrypi,4-model-b", "brcm,bcm2838", "brcm,bcm2837";
36 + model = "Raspberry Pi 4 Model B";
37 + #address-cells = <2>;
41 + device_type = "memory";
42 + reg = <0x0 0x0 0x0>;
46 + bootargs = "8250.nr_uarts=1 cma=64M";
55 + /delete-property/ ethernet;
56 + /delete-property/ intc;
62 + virtgpio: virtgpio {
63 + compatible = "brcm,bcm2835-virtgpio";
66 + firmware = <&firmware>;
72 + pinctrl-names = "default";
73 + pinctrl-0 = <&sdio_pins>;
80 + compatible = "raspberrypi,firmware-gpio";
88 + pinctrl-names = "default";
89 + pinctrl-0 = <&uart0_pins &bt_pins>;
94 + pinctrl-names = "default";
95 + pinctrl-0 = <&uart1_pins>;
100 + pinctrl-names = "default";
101 + pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
102 + cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
105 + compatible = "spidev";
106 + reg = <0>; /* CE0 */
107 + #address-cells = <1>;
109 + spi-max-frequency = <125000000>;
113 + compatible = "spidev";
114 + reg = <1>; /* CE1 */
115 + #address-cells = <1>;
117 + spi-max-frequency = <125000000>;
121 +// =============================================
122 +// Board specific stuff here
126 + sd_io_1v8_reg: sd_io_1v8_reg {
128 + compatible = "regulator-gpio";
129 + vin-supply = <&vdd_5v0_reg>;
130 + regulator-name = "vdd-sd-io";
131 + regulator-min-microvolt = <1800000>;
132 + regulator-max-microvolt = <3300000>;
134 + regulator-always-on;
135 + regulator-settling-time-us = <5000>;
137 + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
138 + states = <1800000 0x1
144 + status = "disabled";
150 + vqmmc-supply = <&sd_io_1v8_reg>;
156 + linux,default-trigger = "mmc0";
157 + gpios = <&gpio 42 0>;
162 + linux,default-trigger = "input";
163 + gpios = <&expgpio 2 0>;
168 + pinctrl-names = "default";
169 + pinctrl-0 = <&audio_pins>;
173 + brcm,pins = <22 23 24 25 26 27>;
174 + brcm,function = <BCM2835_FSEL_ALT0>;
178 + spi0_pins: spi0_pins {
179 + brcm,pins = <9 10 11>;
180 + brcm,function = <BCM2835_FSEL_ALT0>;
183 + spi0_cs_pins: spi0_cs_pins {
185 + brcm,function = <BCM2835_FSEL_GPIO_OUT>;
188 + spi3_pins: spi3_pins {
189 + brcm,pins = <1 2 3>;
190 + brcm,function = <BCM2835_FSEL_ALT3>;
193 + spi3_cs_pins: spi3_cs_pins {
194 + brcm,pins = <0 24>;
195 + brcm,function = <BCM2835_FSEL_GPIO_OUT>;
198 + spi4_pins: spi4_pins {
199 + brcm,pins = <5 6 7>;
200 + brcm,function = <BCM2835_FSEL_ALT3>;
203 + spi4_cs_pins: spi4_cs_pins {
204 + brcm,pins = <4 25>;
205 + brcm,function = <BCM2835_FSEL_GPIO_OUT>;
208 + spi5_pins: spi5_pins {
209 + brcm,pins = <13 14 15>;
210 + brcm,function = <BCM2835_FSEL_ALT3>;
213 + spi5_cs_pins: spi5_cs_pins {
214 + brcm,pins = <12 26>;
215 + brcm,function = <BCM2835_FSEL_GPIO_OUT>;
218 + spi6_pins: spi6_pins {
219 + brcm,pins = <19 20 21>;
220 + brcm,function = <BCM2835_FSEL_ALT3>;
223 + spi6_cs_pins: spi6_cs_pins {
224 + brcm,pins = <18 27>;
225 + brcm,function = <BCM2835_FSEL_GPIO_OUT>;
230 + brcm,function = <BCM2835_FSEL_ALT0>;
235 + brcm,function = <BCM2835_FSEL_ALT0>;
240 + brcm,function = <BCM2835_FSEL_ALT5>;
245 + brcm,function = <BCM2835_FSEL_ALT5>;
249 + brcm,pins = <12 13>;
250 + brcm,function = <BCM2835_FSEL_ALT5>;
254 + brcm,pins = <22 23>;
255 + brcm,function = <BCM2835_FSEL_ALT5>;
259 + brcm,pins = <18 19 20 21>;
260 + brcm,function = <BCM2835_FSEL_ALT0>;
263 + sdio_pins: sdio_pins {
264 + brcm,pins = <34 35 36 37 38 39>;
265 + brcm,function = <BCM2835_FSEL_ALT3>; // alt3 = SD1
266 + brcm,pull = <0 2 2 2 2 2>;
270 + brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0
272 + brcm,function = <0>;
276 + uart0_pins: uart0_pins {
277 + brcm,pins = <32 33>;
278 + brcm,function = <BCM2835_FSEL_ALT3>;
282 + uart1_pins: uart1_pins {
288 + uart2_pins: uart2_pins {
290 + brcm,function = <BCM2835_FSEL_ALT4>;
294 + uart3_pins: uart3_pins {
296 + brcm,function = <BCM2835_FSEL_ALT4>;
300 + uart4_pins: uart4_pins {
302 + brcm,function = <BCM2835_FSEL_ALT4>;
306 + uart5_pins: uart5_pins {
307 + brcm,pins = <12 13>;
308 + brcm,function = <BCM2835_FSEL_ALT4>;
312 + audio_pins: audio_pins {
313 + brcm,pins = <40 41>;
314 + brcm,function = <4>;
319 + pinctrl-names = "default";
320 + pinctrl-0 = <&i2c0_pins>;
321 + clock-frequency = <100000>;
325 + pinctrl-names = "default";
326 + pinctrl-0 = <&i2c1_pins>;
327 + clock-frequency = <100000>;
331 + clock-frequency = <100000>;
335 + pinctrl-names = "default";
336 + pinctrl-0 = <&i2s_pins>;
341 + act_led_gpio = <&act_led>,"gpios:4";
342 + act_led_activelow = <&act_led>,"gpios:8";
343 + act_led_trigger = <&act_led>,"linux,default-trigger";
345 + pwr_led_gpio = <&pwr_led>,"gpios:4";
346 + pwr_led_activelow = <&pwr_led>,"gpios:8";
347 + pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
351 +++ b/arch/arm/boot/dts/bcm2711.dtsi
353 +#include "bcm2838.dtsi"
354 +#include "bcm270x.dtsi"
355 +#include "bcm2708-rpi.dtsi"
359 + /delete-node/ mailbox@7e00b840;
360 + /delete-node/ v3d@7ec00000;
369 + brcm,dma-channel-mask = <0x7ef5>;
373 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
377 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
381 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
385 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
389 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
393 + reg = <0x7e980000 0x10000>,
394 + <0x7e00b200 0x200>;
395 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
396 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
400 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
401 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
404 +++ b/arch/arm/boot/dts/bcm2838.dtsi
406 +// SPDX-License-Identifier: GPL-2.0
407 +#include "bcm283x.dtsi"
409 +#include <dt-bindings/interrupt-controller/arm-gic.h>
410 +#include <dt-bindings/soc/bcm2835-pm.h>
413 + compatible = "brcm,bcm2838", "brcm,bcm2837";
415 + interrupt-parent = <&gicv2>;
418 + ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
419 + <0x7c000000 0x0 0xfc000000 0x02000000>,
420 + <0x40000000 0x0 0xff800000 0x00800000>;
421 + /* Emulate a contiguous 30-bit address range for DMA */
422 + dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
424 + /delete-node/ mailbox@7e00b840;
425 + /delete-node/ interrupt-controller@7e00f300;
427 + local_intc: local_intc@40000000 {
428 + compatible = "brcm,bcm2836-l1-intc";
429 + reg = <0x40000000 0x100>;
432 + gicv2: gic400@40041000 {
433 + interrupt-controller;
434 + #interrupt-cells = <3>;
435 + compatible = "arm,gic-400";
436 + reg = <0x40041000 0x1000>,
437 + <0x40042000 0x2000>,
438 + <0x40046000 0x2000>,
439 + <0x40048000 0x2000>;
442 + thermal: thermal@7d5d2200 {
443 + compatible = "brcm,avs-tmon-bcm2838";
444 + reg = <0x7d5d2200 0x2c>;
445 + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
446 + interrupt-names = "tmon";
447 + clocks = <&clocks BCM2835_CLOCK_TSENS>;
448 + #thermal-sensor-cells = <0>;
452 + pm: watchdog@7e100000 {
453 + reg = <0x7e100000 0x114>,
459 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
462 + uart2: serial@7e201400 {
463 + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
464 + reg = <0x7e201400 0x200>;
465 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
466 + clocks = <&clocks BCM2835_CLOCK_UART>,
467 + <&clocks BCM2835_CLOCK_VPU>;
468 + clock-names = "uartclk", "apb_pclk";
469 + arm,primecell-periphid = <0x00241011>;
470 + status = "disabled";
473 + uart3: serial@7e201600 {
474 + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
475 + reg = <0x7e201600 0x200>;
476 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
477 + clocks = <&clocks BCM2835_CLOCK_UART>,
478 + <&clocks BCM2835_CLOCK_VPU>;
479 + clock-names = "uartclk", "apb_pclk";
480 + arm,primecell-periphid = <0x00241011>;
481 + status = "disabled";
484 + uart4: serial@7e201800 {
485 + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
486 + reg = <0x7e201800 0x200>;
487 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
488 + clocks = <&clocks BCM2835_CLOCK_UART>,
489 + <&clocks BCM2835_CLOCK_VPU>;
490 + clock-names = "uartclk", "apb_pclk";
491 + arm,primecell-periphid = <0x00241011>;
492 + status = "disabled";
495 + uart5: serial@7e201a00 {
496 + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
497 + reg = <0x7e201a00 0x200>;
498 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
499 + clocks = <&clocks BCM2835_CLOCK_UART>,
500 + <&clocks BCM2835_CLOCK_VPU>;
501 + clock-names = "uartclk", "apb_pclk";
502 + arm,primecell-periphid = <0x00241011>;
503 + status = "disabled";
507 + reg = <0x7e204000 0x0200>;
508 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
511 + spi3: spi@7e204600 {
512 + compatible = "brcm,bcm2835-spi";
513 + reg = <0x7e204600 0x0200>;
514 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
515 + clocks = <&clocks BCM2835_CLOCK_VPU>;
516 + #address-cells = <1>;
518 + status = "disabled";
521 + spi4: spi@7e204800 {
522 + compatible = "brcm,bcm2835-spi";
523 + reg = <0x7e204800 0x0200>;
524 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
525 + clocks = <&clocks BCM2835_CLOCK_VPU>;
526 + #address-cells = <1>;
528 + status = "disabled";
531 + spi5: spi@7e204a00 {
532 + compatible = "brcm,bcm2835-spi";
533 + reg = <0x7e204a00 0x0200>;
534 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
535 + clocks = <&clocks BCM2835_CLOCK_VPU>;
536 + #address-cells = <1>;
538 + status = "disabled";
541 + spi6: spi@7e204c00 {
542 + compatible = "brcm,bcm2835-spi";
543 + reg = <0x7e204c00 0x0200>;
544 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
545 + clocks = <&clocks BCM2835_CLOCK_VPU>;
546 + #address-cells = <1>;
548 + status = "disabled";
551 + i2c3: i2c@7e205600 {
552 + compatible = "brcm,bcm2835-i2c";
553 + reg = <0x7e205600 0x200>;
554 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
555 + clocks = <&clocks BCM2835_CLOCK_VPU>;
556 + #address-cells = <1>;
558 + status = "disabled";
561 + i2c4: i2c@7e205800 {
562 + compatible = "brcm,bcm2835-i2c";
563 + reg = <0x7e205800 0x200>;
564 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
565 + clocks = <&clocks BCM2835_CLOCK_VPU>;
566 + #address-cells = <1>;
568 + status = "disabled";
571 + i2c5: i2c@7e205a00 {
572 + compatible = "brcm,bcm2835-i2c";
573 + reg = <0x7e205a00 0x200>;
574 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
575 + clocks = <&clocks BCM2835_CLOCK_VPU>;
576 + #address-cells = <1>;
578 + status = "disabled";
581 + i2c6: i2c@7e205c00 {
582 + compatible = "brcm,bcm2835-i2c";
583 + reg = <0x7e205c00 0x200>;
584 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
585 + clocks = <&clocks BCM2835_CLOCK_VPU>;
586 + #address-cells = <1>;
588 + status = "disabled";
591 + pixelvalve@7e206000 {
592 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
595 + pixelvalve@7e207000 {
596 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
599 + emmc2: emmc2@7e340000 {
600 + compatible = "brcm,bcm2711-emmc2";
602 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
603 + clocks = <&clocks BCM2838_CLOCK_EMMC2>;
604 + reg = <0x7e340000 0x100>;
608 + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
611 + pixelvalve@7e807000 {
612 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
618 + * N.B. the A72 PMU support only exists in arch/arm64, hence
619 + * the fallback to the A53 version.
621 + compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
622 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
623 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
624 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
625 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
629 + compatible = "arm,armv7-timer";
630 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
631 + IRQ_TYPE_LEVEL_LOW)>,
632 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
633 + IRQ_TYPE_LEVEL_LOW)>,
634 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
635 + IRQ_TYPE_LEVEL_LOW)>,
636 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
637 + IRQ_TYPE_LEVEL_LOW)>;
638 + arm,cpu-registers-not-fw-configured;
643 + #address-cells = <1>;
645 + enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
648 + device_type = "cpu";
649 + compatible = "arm,cortex-a72";
651 + enable-method = "spin-table";
652 + cpu-release-addr = <0x0 0x000000d8>;
656 + device_type = "cpu";
657 + compatible = "arm,cortex-a72";
659 + enable-method = "spin-table";
660 + cpu-release-addr = <0x0 0x000000e0>;
664 + device_type = "cpu";
665 + compatible = "arm,cortex-a72";
667 + enable-method = "spin-table";
668 + cpu-release-addr = <0x0 0x000000e8>;
672 + device_type = "cpu";
673 + compatible = "arm,cortex-a72";
675 + enable-method = "spin-table";
676 + cpu-release-addr = <0x0 0x000000f0>;
681 + compatible = "simple-bus";
682 + #address-cells = <1>;
684 + ranges = <0x7c500000 0x0 0xfc500000 0x03300000>,
685 + <0x40000000 0x0 0xff800000 0x00800000>;
686 + dma-ranges = <0x00000000 0x0 0x00000000 0x3c000000>;
688 + v3d: v3d@7ec04000 {
689 + compatible = "brcm,2711-v3d";
691 + <0x7ec00000 0x4000>,
692 + <0x7ec04000 0x4000>;
693 + reg-names = "hub", "core0";
695 + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
696 + resets = <&pm BCM2835_RESET_V3D>;
697 + clocks = <&clocks BCM2835_CLOCK_V3D>;
698 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
704 + compatible = "simple-bus";
705 + #address-cells = <2>;
708 + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
709 + <0x0 0x40000000 0x0 0xff800000 0x00800000>,
710 + <0x6 0x00000000 0x6 0x00000000 0x40000000>,
711 + <0x0 0x00000000 0x0 0x00000000 0xfc000000>;
712 + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>;
714 + pcie_0: pcie@7d500000 {
715 + reg = <0x0 0x7d500000 0x9310>,
716 + <0x0 0x7e00f300 0x20>;
718 + msi-parent = <&pcie_0>;
719 + #address-cells = <3>;
720 + #interrupt-cells = <1>;
722 + bus-range = <0x0 0x01>;
723 + compatible = "brcm,bcm7211-pcie", "brcm,bcm7445-pcie",
724 + "brcm,pci-plat-dev";
725 + max-link-speed = <2>;
726 + tot-num-pcie = <1>;
727 + linux,pci-domain = <0>;
728 + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
729 + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
730 + interrupt-names = "pcie", "msi";
731 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
732 + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
733 + IRQ_TYPE_LEVEL_HIGH
734 + 0 0 0 2 &gicv2 GIC_SPI 144
735 + IRQ_TYPE_LEVEL_HIGH
736 + 0 0 0 3 &gicv2 GIC_SPI 145
737 + IRQ_TYPE_LEVEL_HIGH
738 + 0 0 0 4 &gicv2 GIC_SPI 146
739 + IRQ_TYPE_LEVEL_HIGH>;
741 + /* Map outbound accesses from scb:0x6_00000000-03ffffff
742 + * to pci:0x0_f8000000-fbffffff
744 + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
746 + /* Map inbound accesses from pci:0x0_00000000..ffffffff
747 + * to scb:0x0_00000000-ffffffff
749 + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
754 + genet: genet@7d580000 {
755 + compatible = "brcm,genet-v5";
756 + reg = <0x0 0x7d580000 0x10000>;
758 + #address-cells = <0x1>;
759 + #size-cells = <0x1>;
760 + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
761 + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
762 + phy-handle = <&phy1>;
763 + phy-mode = "rgmii";
765 + #address-cells = <0x0>;
766 + #size-cells = <0x1>;
767 + compatible = "brcm,genet-mdio-v5";
769 + reg-names = "mdio";
770 + phy1: genet-phy@0 {
772 + "ethernet-phy-ieee802.3-c22";
773 + /* No interrupts - use PHY_POLL */
774 + max-speed = <1000>;
780 + xhci: xhci@7e9c0000 {
781 + compatible = "generic-xhci";
782 + status = "disabled";
783 + reg = <0x0 0x7e9c0000 0x100000>;
784 + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
787 + vchiq: mailbox@7e00b840 {
788 + compatible = "brcm,bcm2838-vchiq";
789 + reg = <0 0x7e00b840 0x3c>;
790 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
793 + hevc-decoder@7eb00000 {
794 + compatible = "raspberrypi,argon-hevc-decoder";
795 + reg = <0x0 0x7eb00000 0x10000>;
799 + argon-local-intc@7eb10000 {
800 + compatible = "raspberrypi,argon-local-intc";
801 + reg = <0x0 0x7eb10000 0x1000>;
803 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
806 + h264-decoder@7eb20000 {
807 + compatible = "raspberrypi,argon-h264-decoder";
808 + reg = <0x0 0x7eb20000 0x10000>;
812 + vp9-decoder@7eb30000 {
813 + compatible = "raspberrypi,argon-vp9-decoder";
814 + reg = <0x0 0x7eb30000 0x10000>;
821 + clock-frequency = <54000000>;
825 + compatible = "brcm,bcm2838-cprman";
829 + coefficients = <(-487) 410040>;
833 + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
837 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
841 + gpclk0_gpio49: gpclk0_gpio49 {
843 + brcm,function = <BCM2835_FSEL_ALT1>;
844 + brcm,pull = <BCM2835_PUD_OFF>;
846 + gpclk1_gpio50: gpclk1_gpio50 {
848 + brcm,function = <BCM2835_FSEL_ALT1>;
849 + brcm,pull = <BCM2835_PUD_OFF>;
851 + gpclk2_gpio51: gpclk2_gpio51 {
853 + brcm,function = <BCM2835_FSEL_ALT1>;
854 + brcm,pull = <BCM2835_PUD_OFF>;
857 + i2c0_gpio46: i2c0_gpio46 {
858 + brcm,pins = <46 47>;
859 + brcm,function = <BCM2835_FSEL_ALT0>;
861 + i2c1_gpio46: i2c1_gpio46 {
862 + brcm,pins = <46 47>;
863 + brcm,function = <BCM2835_FSEL_ALT1>;
865 + i2c3_gpio2: i2c3_gpio2 {
867 + brcm,function = <BCM2835_FSEL_ALT5>;
869 + i2c3_gpio4: i2c3_gpio4 {
871 + brcm,function = <BCM2835_FSEL_ALT5>;
873 + i2c4_gpio6: i2c4_gpio6 {
875 + brcm,function = <BCM2835_FSEL_ALT5>;
877 + i2c4_gpio8: i2c4_gpio8 {
879 + brcm,function = <BCM2835_FSEL_ALT5>;
881 + i2c5_gpio10: i2c5_gpio10 {
882 + brcm,pins = <10 11>;
883 + brcm,function = <BCM2835_FSEL_ALT5>;
885 + i2c5_gpio12: i2c5_gpio12 {
886 + brcm,pins = <12 13>;
887 + brcm,function = <BCM2835_FSEL_ALT5>;
889 + i2c6_gpio0: i2c6_gpio0 {
891 + brcm,function = <BCM2835_FSEL_ALT5>;
893 + i2c6_gpio22: i2c6_gpio22 {
894 + brcm,pins = <22 23>;
895 + brcm,function = <BCM2835_FSEL_ALT5>;
897 + i2c_slave_gpio8: i2c_slave_gpio8 {
898 + brcm,pins = <8 9 10 11>;
899 + brcm,function = <BCM2835_FSEL_ALT3>;
902 + jtag_gpio48: jtag_gpio48 {
903 + brcm,pins = <48 49 50 51 52 53>;
904 + brcm,function = <BCM2835_FSEL_ALT4>;
907 + mii_gpio28: mii_gpio28 {
908 + brcm,pins = <28 29 30 31>;
909 + brcm,function = <BCM2835_FSEL_ALT4>;
911 + mii_gpio36: mii_gpio36 {
912 + brcm,pins = <36 37 38 39>;
913 + brcm,function = <BCM2835_FSEL_ALT5>;
916 + pcm_gpio50: pcm_gpio50 {
917 + brcm,pins = <50 51 52 53>;
918 + brcm,function = <BCM2835_FSEL_ALT2>;
921 + pwm0_gpio52: pwm0_gpio52 {
923 + brcm,function = <BCM2835_FSEL_ALT1>;
924 + brcm,pull = <BCM2835_PUD_OFF>;
926 + pwm1_gpio53: pwm1_gpio53 {
928 + brcm,function = <BCM2835_FSEL_ALT1>;
929 + brcm,pull = <BCM2835_PUD_OFF>;
932 + /* The following group consists of:
936 + rgmii_gpio35: rgmii_gpio35 {
937 + brcm,pins = <35 36>;
938 + brcm,function = <BCM2835_FSEL_ALT4>;
940 + rgmii_irq_gpio34: rgmii_irq_gpio34 {
942 + brcm,function = <BCM2835_FSEL_ALT5>;
944 + rgmii_irq_gpio39: rgmii_irq_gpio39 {
946 + brcm,function = <BCM2835_FSEL_ALT4>;
948 + rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
949 + brcm,pins = <28 29>;
950 + brcm,function = <BCM2835_FSEL_ALT5>;
952 + rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
953 + brcm,pins = <37 38>;
954 + brcm,function = <BCM2835_FSEL_ALT4>;
957 + spi0_gpio46: spi0_gpio46 {
958 + brcm,pins = <46 47 48 49>;
959 + brcm,function = <BCM2835_FSEL_ALT2>;
961 + spi2_gpio46: spi2_gpio46 {
962 + brcm,pins = <46 47 48 49 50>;
963 + brcm,function = <BCM2835_FSEL_ALT5>;
965 + spi3_gpio0: spi3_gpio0 {
966 + brcm,pins = <0 1 2 3>;
967 + brcm,function = <BCM2835_FSEL_ALT3>;
969 + spi4_gpio4: spi4_gpio4 {
970 + brcm,pins = <4 5 6 7>;
971 + brcm,function = <BCM2835_FSEL_ALT3>;
973 + spi5_gpio12: spi5_gpio12 {
974 + brcm,pins = <12 13 14 15>;
975 + brcm,function = <BCM2835_FSEL_ALT3>;
977 + spi6_gpio18: spi6_gpio18 {
978 + brcm,pins = <18 19 20 21>;
979 + brcm,function = <BCM2835_FSEL_ALT3>;
982 + uart2_gpio0: uart2_gpio0 {
984 + brcm,function = <BCM2835_FSEL_ALT4>;
985 + brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
987 + uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
989 + brcm,function = <BCM2835_FSEL_ALT4>;
990 + brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
992 + uart3_gpio4: uart3_gpio4 {
994 + brcm,function = <BCM2835_FSEL_ALT4>;
995 + brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
997 + uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
999 + brcm,function = <BCM2835_FSEL_ALT4>;
1000 + brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1002 + uart4_gpio8: uart4_gpio8 {
1003 + brcm,pins = <8 9>;
1004 + brcm,function = <BCM2835_FSEL_ALT4>;
1005 + brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1007 + uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1008 + brcm,pins = <10 11>;
1009 + brcm,function = <BCM2835_FSEL_ALT4>;
1010 + brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1012 + uart5_gpio12: uart5_gpio12 {
1013 + brcm,pins = <12 13>;
1014 + brcm,function = <BCM2835_FSEL_ALT4>;
1015 + brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
1017 + uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1018 + brcm,pins = <14 15>;
1019 + brcm,function = <BCM2835_FSEL_ALT4>;
1020 + brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
1025 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1029 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1033 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1034 + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1038 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1042 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1046 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1050 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1054 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1058 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1062 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1066 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1070 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1074 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1075 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1076 + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1077 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1081 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1085 + compatible = "brcm,bcm2838-rng200";
1089 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1093 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1097 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1098 + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1099 + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1100 + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1101 + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1102 + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1103 + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1104 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 7 */
1105 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 8 */
1106 + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 9 */
1107 + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite 10 */
1108 + /* DMA4 - 40 bit DMA engines */
1109 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 11 */
1110 + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 12 */
1111 + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4 13 */
1112 + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4 14 */
1113 + interrupt-names = "dma0",
1128 + brcm,dma-channel-mask = <0x7ef5>;